fault_injection_async25_paper/fault_injection_async25.bib

@techreport{manohar_open_2019,
	title = {An {Open} {Source} {Design} {Flow} for {Asynchronous} {Circuits}},
	url = {https://apps.dtic.mil/sti/citations/AD1075807},
	abstract = {There have been a number of small-scale and large-scale technology demonstrations of asynchronous circuits, showing that they have benefits in performance and power efficiency in a variety of application domains. Most recently, asynchronous circuits were used in the TrueNorth neuromorphic chip to achieve unprecedented energy-efficiency for neuromorphic systems. However, these circuits cannot be easily adopted, because commercially available design tools do not support asynchronous logic. As part of the DARPA ERI effort, we are addressing this challenge by developing a set of open-source design tools for asynchronous circuits.},
	language = {en},
	urldate = {2023-03-22},
	author = {Manohar, Rajit},
	year = {2019},
	note = {Section: Technical Reports},
	file = {Manohar - An Open-Source Design Flow for Asynchronous Circui.pdf:/home/fabian/Zotero/storage/V3WLFW8A/Manohar - An Open-Source Design Flow for Asynchronous Circui.pdf:application/pdf},
}

@inproceedings{behal_automated_2021,
	title = {An {Automated} {Setup} for {Large}-{Scale} {Simulation}-{Based} {Fault}-{Injection} {Experiments} on {Asynchronous} {Digital} {Circuits}},
	doi = {10.1109/DSD53832.2021.00087},
	abstract = {Experimental fault injection is an essential tool in the assessment and verification of fault-tolerance properties. Often, in these experiments it is impossible to reasonably cover the huge parameter space spanned by target state and fault parameters, and compromises or restrictions must be made. This is even more pronounced for asynchronous circuits where a convenient discretization of time through a synchronous clock is not possible. In this paper we present a fault-injection toolset that allows for a very efficient injection and data processing, thus bringing studies with many billions of meaningful injections into asynchronous targets within reach. The key ingredients of our solution are an auto-setup feature capable of optimizing parameter values, seamless distribution of the simulation load to many host computers, and efficient arrangement of the important settings and readings in a database. We will use the example of a comparative study of different asynchronous pipeline styles to motivate the need for such an approach and illustrate its benefits.},
	booktitle = {2021 24th {Euromicro} {Conference} on {Digital} {System} {Design} ({DSD})},
	author = {Behal, Patrick and Huemer, Florian and Najvirt, Robert and Steininger, Andreas},
	month = sep,
	year = {2021},
	keywords = {asynchronous circuits, Circuit faults, Data models, Databases, fault injection, fault-tolerance assessment, Integrated circuit modeling, Pipelines, Task analysis, tool chain, Tools},
	pages = {541--548},
	file = {Behal et al_2021_An Automated Setup for Large-Scale Simulation-Based Fault-Injection Experiments.pdf:/home/fabian/Zotero/storage/P2Z8XV9J/Behal et al_2021_An Automated Setup for Large-Scale Simulation-Based Fault-Injection Experiments.pdf:application/pdf;IEEE Xplore Abstract Record:/home/fabian/Zotero/storage/J2YJQQEM/9556468.html:text/html},
}

@inproceedings{huemer_identification_2020,
	title = {Identification and {Confinement} of {Fault} {Sensitivity} {Windows} in {QDI} {Logic}},
	doi = {10.1109/Austrochip51129.2020.9232985},
	abstract = {Asynchronous, specifically QDI circuits are known to exhibit high resilience against faults affecting the timing. At the same time, their event based operation principle makes them susceptible to glitches. While synchronous circuits obtain high resilience through temporal masking that is established through the sampling of data by flip flops, asynchronous designs, by trying to be flexible about the phases of data validity, often have lower masking capabilities. Consequently, previous work has proposed to narrow down the windows in which data changes are accepted, in order to improve the temporal masking in QDI designs.In this paper we study the natural resilience of different QDI templates in more detail and quantitatively determine the windows of vulnerability through extensive fault injection experiments in simulation. To this end we propose a novel way of visualizing and analyzing the sensitivity windows that aids in identifying the key dependencies and vulnerabilities. In addition we introduce and evaluate two low-cost extensions for the pipeline registers which allow either to stall the operation in case a glitch creates an illegal symbol, or to prevent the creation of an illegal symbol in the first place.},
	booktitle = {2020 {Austrochip} {Workshop} on {Microelectronics} ({Austrochip})},
	author = {Huemer, Florian and Najvirt, Robert and Steininger, Andreas},
	month = oct,
	year = {2020},
	keywords = {Protocols, Circuit faults, Pipelines, Integrated circuit modeling, Logic gates, Rails, Resilience},
	pages = {29--36},
	file = {Huemer et al_2020_Identification and Confinement of Fault Sensitivity Windows in QDI Logic.pdf:/home/fabian/Zotero/storage/HEG9QF34/Huemer et al_2020_Identification and Confinement of Fault Sensitivity Windows in QDI Logic.pdf:application/pdf;Huemer et al. - 2020 - Identification and Confinement of Fault Sensitivit.pdf:/home/fabian/Zotero/storage/RJLXL75V/Huemer et al. - 2020 - Identification and Confinement of Fault Sensitivit.pdf:application/pdf;IEEE Xplore Abstract Record:/home/fabian/Zotero/storage/IQUBBXXK/9232985.html:text/html},
}

@inproceedings{behal_towards_2021,
	title = {Towards {Explaining} the {Fault} {Sensitivity} of {Different} {QDI} {Pipeline} {Styles}},
	doi = {10.1109/ASYNC48570.2021.00012},
	abstract = {Asynchronous circuits, specifically those using a quasi delay-insensitive (QDI) implementation are known for their high resilience against timing uncertainties. However, their event-based operation principle impedes their temporal masking capability, making them more susceptible to fault-induced transitions caused by single event transients. While synchronous circuits obtain high resilience through temporal masking that is established through the sampling of data by flip flops, asynchronous circuits, by design must be flexible about the phases of data validity leaving a larger attack surface for faults. Consequently, previous work has proposed to narrow down the windows in which data changes are accepted, in order to improve the temporal masking in QDI designs.In this paper, we analyze the fault sensitivity of asynchronous QDI circuits when subjected to single event transients. We do so by performing extensive fault injection experiments into different buffer styles to identify parameters that are the main contributors to the fault sensitivity of the circuit and compare their resilience.For that purpose, we use two variants of a multiplier circuit as target circuits. One with the shift and add operations arranged in a linear pipeline, and another one with an internal ring structure that computes the result iteratively, yielding designs with the same logic and buffer implementations, yet very different modes of operation. By varying the buffer styles, we are able to show the difference in robustness as well as the effectiveness of fault mitigation techniques inherent in some buffer styles.},
	booktitle = {2021 27th {IEEE} {International} {Symposium} on {Asynchronous} {Circuits} and {Systems} ({ASYNC})},
	author = {Behal, Patrick and Huemer, Florian and Najvirt, Robert and Steininger, Andreas and Tabassam, Zaheer},
	month = sep,
	year = {2021},
	note = {ISSN: 2643-1483},
	keywords = {Timing, Circuit faults, Pipelines, Integrated circuit modeling, asynchronous circuits, fault-tolerance, Sensitivity, SET, Single event transients, Uncertainty},
	pages = {25--33},
	file = {Behal et al_2021_Towards Explaining the Fault Sensitivity of Different QDI Pipeline Styles.pdf:/home/fabian/Zotero/storage/IFFBY78C/Behal et al_2021_Towards Explaining the Fault Sensitivity of Different QDI Pipeline Styles.pdf:application/pdf;IEEE Xplore Abstract Record:/home/fabian/Zotero/storage/Q4JM4CNN/9565441.html:text/html},
}

@phdthesis{huemer_contributions_2022,
	type = {Thesis},
	title = {Contributions to efficiency and robustness of quasi delay-insensitive circuits},
	url = {https://repositum.tuwien.at/handle/20.500.12708/136294},
	abstract = {In the field of digital integrated circuits asynchronous and especially quasi delay-insensitive (QDI) designs are known to have a high robustness against process, voltage and temperature variations – an increasingly desired property. This is because for QDI designs only very few timing assumptions and constraints are necessary to guarantee the correct behavior of a circuit, which is in strong contrast to the rigid timing scheme of the traditional synchronous design style. This characteristic key-property opens up many interesting and highly relevant application areas – two of are the focus of this thesis. The inherent robustness against timing variations makes QDI design styles and techniques (i) perfectly suited for constructing delay-insensitive (DI) communication channels for global inter- or intra-chip interconnect and (ii) a promising choice for the design of fault-tolerant systems. The first part of this work is, hence, devoted to the investigation of efficient ways to transmit information in a DI way, as well as the design of interface components that allow the integration of asynchronous circuits in otherwise synchronous systems. We provide a comprehensive analysis of available protocols and data encoding schemes and complement them with our own contributions to the field. The second part, then, explores the fault-tolerance aspects of QDI design. In particular, we analyze the effects of transient faults, investigate fault-mitigation strategies from literature and present and evaluate our own techniques. For that purpose, a comprehensive tool set to generate, analyze and simulate asynchronous circuits has been developed.},
	language = {en},
	urldate = {2023-05-18},
	school = {Technische Universität Wien},
	author = {Huemer, Florian Ferdinand},
	year = {2022},
	doi = {10.34726/hss.2022.107641},
	note = {Accepted: 2022-12-09T10:32:19Z},
	file = {Huemer Florian Ferdinand - 2022 - Contributions to efficiency and robustness of...pdf:/home/fabian/Zotero/storage/B6678I8B/Huemer Florian Ferdinand - 2022 - Contributions to efficiency and robustness of...pdf:application/pdf},
}

@article{altera_introduction_2013,
	title = {Introduction to {Single}-{Event} {Upsets}},
	url = {https://cdrdv2-public.intel.com/650466/wp-01206-introduction-single-event-upsets.pdf},
	abstract = {This paper provides an overview of single event upsets (SEU), the capabilities provided in FPGAs to mitigate the effects of SEU, techniques that can be incorporated in user designs to mitigate the effects of SEU, and how tools and intellectual property (IP) can be used to validate a design to ensure high levels of tolerance for SEU.},
	journal = {WP-01206-1.0},
	author = {Altera},
	month = sep,
	year = {2013},
	file = {Altera_2013_Introduction to Single-Event Upsets.pdf:/home/fabian/Zotero/storage/CDP9CDNW/Altera_2013_Introduction to Single-Event Upsets.pdf:application/pdf},
}

@inproceedings{tabassam__2023,
	title = {ζ: {A} {Novel} {Approach} for {Mitigating} {Single} {Event} {Transient} {Effects} in {Quasi} {Delay} {Insensitive} {Logic}},
	shorttitle = {ζ},
	url = {https://ieeexplore.ieee.org/abstract/document/10239589},
	doi = {10.1109/ASYNC58294.2023.10239589},
	abstract = {Due to their flexible data accepting windows Quasi Delay-Insensitive (QDI) circuits are susceptible to environmental effects such as single event transients (SETs). Their mode of operation often demands that the combinational logic of such circuits contains storage elements in the form of Muller C-element (MCE)s. This fact makes it likely for an SETs to be converted into an single event upset (SEU). Nevertheless, most of the available approaches in literature focus on hardening the butter elements between combinational logic blocks to mitigate the effects of SETs with less emphasis on the logic itself. In this work, we first review existing techniques addressing SETs in combinational logic. We analyze and compare them to a non-resilient basic QDI circuit template. We conclude that these techniques are not effective compared to this basic template because the addition of extra circuitry increases the susceptibility of the overall circuit towards SETs. Some of these techniques are only valid with extra assumptions, one is, exempting the mitigating circuit part from fault injection. Another main limitation is concerning the way in which the circuits flush out faults in the combinational logic. The proposed techniques can easily lead to a violation of the handshake protocol by forcing all combinational signals to zero, which may introduce an additional null phase depending on the next stage. After thorough analysis, we present a technique to flush the erroneous value within the combinational logic while maintaining the remaining part of combinational logic. This flushing does not require extra combinational cycles for re-computing the logic value. We combine our novel flushing approach with a resilient butter style to make the overall circuits highly resilient towards SETs. To facilitate a fair comparison we also utilize this resilient butter template with other combinational logic flushing techniques. For the evaluation of the results, we simulate all techniques with a 16-bit multiplier circuit realized with the NanGate 15nm library. The extensive fault injection experiments show the resilience of our novel combinational logic flushing approach.},
	urldate = {2024-12-17},
	booktitle = {2023 28th {IEEE} {International} {Symposium} on {Asynchronous} {Circuits} and {Systems} ({ASYNC})},
	author = {Tabassam, Zaheer and Steininger, Andreas and Najvirt, Robert and Huemer, Florian},
	month = jul,
	year = {2023},
	note = {ISSN: 2643-1483},
	keywords = {Throughput, Protocols, Logic gates, Single event transients, Codes, combinational logic flushing, Dairy products, quasi delay insensitive, single event transients, Single event upsets},
	pages = {48--57},
	file = {Full Text PDF:/home/fabian/Zotero/storage/7TZVQIIW/Tabassam et al. - 2023 - ζ A Novel Approach for Mitigating Single Event Transient Effects in Quasi Delay Insensitive Logic.pdf:application/pdf;IEEE Xplore Abstract Record:/home/fabian/Zotero/storage/L7XLXJHK/10239589.html:text/html},
}

@phdthesis{schwendinger_evaluation_2022,
	type = {Thesis},
	title = {Evaluation of different tools for design and fault-injection of asynchronous circuits},
	copyright = {http://rightsstatements.org/vocab/InC/1.0/},
	url = {https://repositum.tuwien.at/handle/20.500.12708/80366},
	abstract = {Asynchronous circuits (ACs) are currently aced out by synchronous circuits (SCs) in industry purposes. Nevertheless there were prominent innovations utilizing ACs in the field of brain-inspired hardware like SpiNNaker, Neurogrid and the TrueNorth. Researchers claim also a theoretical performance advantage of ACs in terms of speed and energy efficiency. However, one handicap when designing ACs is the current lack of tools designated especially to AC design. Often tools originally targeted to SC design are (mis)used. This thesis presents two flows designed especially to AC design. The first one is developed by the Embedded Computing Systems (ECS) group at TU Wien. It is focused on fault-injection experiments at gate level, but provides also Python scripts for high level AC generation. The second one is the Asynchronous Circuit Toolkit (ACT) developed by the asynchronous VLSI and architecture (asyncVLSI) group at YaleUniversity. It aims for a complete coverage of chip design from high level description to fabricable GDSII format. This thesis will extensively present both these flows, and then proceed with their integration into a combined flow. In particular a translation script of the production rule set (PRS) format in its concrete implementation at TU Wien to ACT has been developed. Additionally the fault-injection engine, which is part of the TU Wien flow, has been overhauled to now also support the Prsim simulation software, which is part of the Yale flow. Afterwards, as a proof of concept, for the integrated flow about a million fault-injections have been performed with Modelsim, which was previously without alternative for the TU Wien flow, and Prsim. While one should initially expect the two tools to deliver the same results, mismatches are spotted that could be tracked back to aspects where Modelsim and Prsim operate differently.},
	language = {en},
	urldate = {2025-01-03},
	school = {Technische Universität Wien},
	author = {Schwendinger, Martin},
	year = {2022},
	doi = {10.34726/hss.2022.98624},
	note = {Accepted: 2022-09-16T07:23:54Z
Journal Abbreviation: Evaluierung von verschiedenen Tools für Design und Fehlerinjektion von Asynchronen Schaltungen},
	file = {Full Text PDF:/home/fabian/Zotero/storage/9EBJ7BI9/Schwendinger - 2022 - Evaluation of different tools for design and fault-injection of asynchronous circuits.pdf:application/pdf},
}