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@techreport{manohar_open_2019,
title = {An {Open} {Source} {Design} {Flow} for {Asynchronous} {Circuits}},
url = {https://apps.dtic.mil/sti/citations/AD1075807},
abstract = {There have been a number of small-scale and large-scale technology demonstrations of asynchronous circuits, showing that they have benefits in performance and power efficiency in a variety of application domains. Most recently, asynchronous circuits were used in the TrueNorth neuromorphic chip to achieve unprecedented energy-efficiency for neuromorphic systems. However, these circuits cannot be easily adopted, because commercially available design tools do not support asynchronous logic. As part of the DARPA ERI effort, we are addressing this challenge by developing a set of open-source design tools for asynchronous circuits.},
language = {en},
urldate = {2023-03-22},
author = {Manohar, Rajit},
year = {2019},
note = {Section: Technical Reports},
file = {Manohar - An Open-Source Design Flow for Asynchronous Circui.pdf:/home/fabian/Zotero/storage/V3WLFW8A/Manohar - An Open-Source Design Flow for Asynchronous Circui.pdf:application/pdf},
@article{alteraIntroductionSingleEventUpsets2013,
title = {Introduction to {{Single-Event Upsets}}},
author = {Altera},
year = {2013},
month = sep,
journal = {WP-01206-1.0},
abstract = {This paper provides an overview of single event upsets (SEU), the capabilities provided in FPGAs to mitigate the effects of SEU, techniques that can be incorporated in user designs to mitigate the effects of SEU, and how tools and intellectual property (IP) can be used to validate a design to ensure high levels of tolerance for SEU.},
file = {/home/fabian/Zotero/storage/CDP9CDNW/Altera_2013_Introduction to Single-Event Upsets.pdf}
}
@inproceedings{behal_automated_2021,
title = {An {Automated} {Setup} for {Large}-{Scale} {Simulation}-{Based} {Fault}-{Injection} {Experiments} on {Asynchronous} {Digital} {Circuits}},
doi = {10.1109/DSD53832.2021.00087},
abstract = {Experimental fault injection is an essential tool in the assessment and verification of fault-tolerance properties. Often, in these experiments it is impossible to reasonably cover the huge parameter space spanned by target state and fault parameters, and compromises or restrictions must be made. This is even more pronounced for asynchronous circuits where a convenient discretization of time through a synchronous clock is not possible. In this paper we present a fault-injection toolset that allows for a very efficient injection and data processing, thus bringing studies with many billions of meaningful injections into asynchronous targets within reach. The key ingredients of our solution are an auto-setup feature capable of optimizing parameter values, seamless distribution of the simulation load to many host computers, and efficient arrangement of the important settings and readings in a database. We will use the example of a comparative study of different asynchronous pipeline styles to motivate the need for such an approach and illustrate its benefits.},
booktitle = {2021 24th {Euromicro} {Conference} on {Digital} {System} {Design} ({DSD})},
author = {Behal, Patrick and Huemer, Florian and Najvirt, Robert and Steininger, Andreas},
month = sep,
year = {2021},
keywords = {Databases, Circuit faults, Pipelines, Integrated circuit modeling, asynchronous circuits, Data models, fault injection, fault-tolerance assessment, Task analysis, tool chain, Tools},
pages = {541--548},
file = {Behal et al_2021_An Automated Setup for Large-Scale Simulation-Based Fault-Injection Experiments.pdf:/home/fabian/Zotero/storage/P2Z8XV9J/Behal et al_2021_An Automated Setup for Large-Scale Simulation-Based Fault-Injection Experiments.pdf:application/pdf;IEEE Xplore Abstract Record:/home/fabian/Zotero/storage/J2YJQQEM/9556468.html:text/html},
@inproceedings{bainbridgeGlitchSensitivityDefense2009,
title = {Glitch {{Sensitivity}} and {{Defense}} of {{Quasi Delay-Insensitive Network-on-Chip Links}}},
booktitle = {2009 15th {{IEEE Symposium}} on {{Asynchronous Circuits}} and {{Systems}}},
author = {Bainbridge, William John and Salisbury, Sean James},
year = {2009},
month = may,
pages = {35--44},
issn = {1522-8681},
doi = {10.1109/ASYNC.2009.18},
urldate = {2025-01-04},
abstract = {To the casual observer, glitches occurring in quasi delay-insensitive logic would appear to cause incorrect operation and render the circuits unusable. This paper presents an informal analysis of the effects of glitches occurring on the long interconnect wires connecting logical units of a network-on-chip (NoC) using quasi delay-insensitive (QDI) techniques. This is followed by the introduction and analysis of a set of techniques to reduce the likelihood and impact of such hazards affecting the circuit. Post layout area and performance impacts are presented for a 90 nm process.},
keywords = {Asynchronous,Asynchronous circuits,Delay effects,Delay Insensitive,Electromagnetic coupling,Electromagnetic interference,Glitch,Hazard,Hazards,Integrated circuit interconnections,Logic circuits,Network-on-a-chip,Network-on-Chip,NoC,Pipelines,QDI,Wires},
file = {/home/fabian/Zotero/storage/S63EJBW8/Bainbridge and Salisbury - 2009 - Glitch Sensitivity and Defense of Quasi Delay-Insensitive Network-on-Chip Links.pdf;/home/fabian/Zotero/storage/CT84FYAU/5010334.html}
}
@inproceedings{huemer_identification_2020,
title = {Identification and {Confinement} of {Fault} {Sensitivity} {Windows} in {QDI} {Logic}},
doi = {10.1109/Austrochip51129.2020.9232985},
abstract = {Asynchronous, specifically QDI circuits are known to exhibit high resilience against faults affecting the timing. At the same time, their event based operation principle makes them susceptible to glitches. While synchronous circuits obtain high resilience through temporal masking that is established through the sampling of data by flip flops, asynchronous designs, by trying to be flexible about the phases of data validity, often have lower masking capabilities. Consequently, previous work has proposed to narrow down the windows in which data changes are accepted, in order to improve the temporal masking in QDI designs.In this paper we study the natural resilience of different QDI templates in more detail and quantitatively determine the windows of vulnerability through extensive fault injection experiments in simulation. To this end we propose a novel way of visualizing and analyzing the sensitivity windows that aids in identifying the key dependencies and vulnerabilities. In addition we introduce and evaluate two low-cost extensions for the pipeline registers which allow either to stall the operation in case a glitch creates an illegal symbol, or to prevent the creation of an illegal symbol in the first place.},
booktitle = {2020 {Austrochip} {Workshop} on {Microelectronics} ({Austrochip})},
author = {Huemer, Florian and Najvirt, Robert and Steininger, Andreas},
month = oct,
year = {2020},
keywords = {Protocols, Circuit faults, Pipelines, Integrated circuit modeling, Logic gates, Rails, Resilience},
pages = {29--36},
file = {Huemer et al_2020_Identification and Confinement of Fault Sensitivity Windows in QDI Logic.pdf:/home/fabian/Zotero/storage/HEG9QF34/Huemer et al_2020_Identification and Confinement of Fault Sensitivity Windows in QDI Logic.pdf:application/pdf;Huemer et al. - 2020 - Identification and Confinement of Fault Sensitivit.pdf:/home/fabian/Zotero/storage/RJLXL75V/Huemer et al. - 2020 - Identification and Confinement of Fault Sensitivit.pdf:application/pdf;IEEE Xplore Abstract Record:/home/fabian/Zotero/storage/IQUBBXXK/9232985.html:text/html},
@inproceedings{behalAutomatedSetupLargeScale2021,
title = {An {{Automated Setup}} for {{Large-Scale Simulation-Based Fault-Injection Experiments}} on {{Asynchronous Digital Circuits}}},
booktitle = {2021 24th {{Euromicro Conference}} on {{Digital System Design}} ({{DSD}})},
author = {Behal, Patrick and Huemer, Florian and Najvirt, Robert and Steininger, Andreas},
year = {2021},
month = sep,
pages = {541--548},
doi = {10.1109/DSD53832.2021.00087},
abstract = {Experimental fault injection is an essential tool in the assessment and verification of fault-tolerance properties. Often, in these experiments it is impossible to reasonably cover the huge parameter space spanned by target state and fault parameters, and compromises or restrictions must be made. This is even more pronounced for asynchronous circuits where a convenient discretization of time through a synchronous clock is not possible. In this paper we present a fault-injection toolset that allows for a very efficient injection and data processing, thus bringing studies with many billions of meaningful injections into asynchronous targets within reach. The key ingredients of our solution are an auto-setup feature capable of optimizing parameter values, seamless distribution of the simulation load to many host computers, and efficient arrangement of the important settings and readings in a database. We will use the example of a comparative study of different asynchronous pipeline styles to motivate the need for such an approach and illustrate its benefits.},
keywords = {asynchronous circuits,Circuit faults,Data models,Databases,fault injection,fault-tolerance assessment,Integrated circuit modeling,Pipelines,Task analysis,tool chain,Tools},
file = {/home/fabian/Zotero/storage/P2Z8XV9J/Behal et al_2021_An Automated Setup for Large-Scale Simulation-Based Fault-Injection Experiments.pdf;/home/fabian/Zotero/storage/J2YJQQEM/9556468.html}
}
@inproceedings{behal_towards_2021,
title = {Towards {Explaining} the {Fault} {Sensitivity} of {Different} {QDI} {Pipeline} {Styles}},
doi = {10.1109/ASYNC48570.2021.00012},
abstract = {Asynchronous circuits, specifically those using a quasi delay-insensitive (QDI) implementation are known for their high resilience against timing uncertainties. However, their event-based operation principle impedes their temporal masking capability, making them more susceptible to fault-induced transitions caused by single event transients. While synchronous circuits obtain high resilience through temporal masking that is established through the sampling of data by flip flops, asynchronous circuits, by design must be flexible about the phases of data validity leaving a larger attack surface for faults. Consequently, previous work has proposed to narrow down the windows in which data changes are accepted, in order to improve the temporal masking in QDI designs.In this paper, we analyze the fault sensitivity of asynchronous QDI circuits when subjected to single event transients. We do so by performing extensive fault injection experiments into different buffer styles to identify parameters that are the main contributors to the fault sensitivity of the circuit and compare their resilience.For that purpose, we use two variants of a multiplier circuit as target circuits. One with the shift and add operations arranged in a linear pipeline, and another one with an internal ring structure that computes the result iteratively, yielding designs with the same logic and buffer implementations, yet very different modes of operation. By varying the buffer styles, we are able to show the difference in robustness as well as the effectiveness of fault mitigation techniques inherent in some buffer styles.},
booktitle = {2021 27th {IEEE} {International} {Symposium} on {Asynchronous} {Circuits} and {Systems} ({ASYNC})},
author = {Behal, Patrick and Huemer, Florian and Najvirt, Robert and Steininger, Andreas and Tabassam, Zaheer},
month = sep,
year = {2021},
note = {ISSN: 2643-1483},
keywords = {Timing, Circuit faults, Pipelines, Integrated circuit modeling, asynchronous circuits, fault-tolerance, Sensitivity, SET, Single event transients, Uncertainty},
pages = {25--33},
file = {Behal et al_2021_Towards Explaining the Fault Sensitivity of Different QDI Pipeline Styles.pdf:/home/fabian/Zotero/storage/IFFBY78C/Behal et al_2021_Towards Explaining the Fault Sensitivity of Different QDI Pipeline Styles.pdf:application/pdf;IEEE Xplore Abstract Record:/home/fabian/Zotero/storage/Q4JM4CNN/9565441.html:text/html},
@inproceedings{behalExplainingFaultSensitivity2021,
title = {Towards {{Explaining}} the {{Fault Sensitivity}} of {{Different QDI Pipeline Styles}}},
booktitle = {2021 27th {{IEEE International Symposium}} on {{Asynchronous Circuits}} and {{Systems}} ({{ASYNC}})},
author = {Behal, Patrick and Huemer, Florian and Najvirt, Robert and Steininger, Andreas and Tabassam, Zaheer},
year = {2021},
month = sep,
pages = {25--33},
issn = {2643-1483},
doi = {10.1109/ASYNC48570.2021.00012},
abstract = {Asynchronous circuits, specifically those using a quasi delay-insensitive (QDI) implementation are known for their high resilience against timing uncertainties. However, their event-based operation principle impedes their temporal masking capability, making them more susceptible to fault-induced transitions caused by single event transients. While synchronous circuits obtain high resilience through temporal masking that is established through the sampling of data by flip flops, asynchronous circuits, by design must be flexible about the phases of data validity leaving a larger attack surface for faults. Consequently, previous work has proposed to narrow down the windows in which data changes are accepted, in order to improve the temporal masking in QDI designs.In this paper, we analyze the fault sensitivity of asynchronous QDI circuits when subjected to single event transients. We do so by performing extensive fault injection experiments into different buffer styles to identify parameters that are the main contributors to the fault sensitivity of the circuit and compare their resilience.For that purpose, we use two variants of a multiplier circuit as target circuits. One with the shift and add operations arranged in a linear pipeline, and another one with an internal ring structure that computes the result iteratively, yielding designs with the same logic and buffer implementations, yet very different modes of operation. By varying the buffer styles, we are able to show the difference in robustness as well as the effectiveness of fault mitigation techniques inherent in some buffer styles.},
keywords = {asynchronous circuits,Circuit faults,fault-tolerance,Integrated circuit modeling,Pipelines,Sensitivity,SET,Single event transients,Timing,Uncertainty},
file = {/home/fabian/Zotero/storage/IFFBY78C/Behal et al_2021_Towards Explaining the Fault Sensitivity of Different QDI Pipeline Styles.pdf;/home/fabian/Zotero/storage/Q4JM4CNN/9565441.html}
}
@phdthesis{huemer_contributions_2022,
type = {Thesis},
title = {Contributions to efficiency and robustness of quasi delay-insensitive circuits},
url = {https://repositum.tuwien.at/handle/20.500.12708/136294},
abstract = {In the field of digital integrated circuits asynchronous and especially quasi delay-insensitive (QDI) designs are known to have a high robustness against process, voltage and temperature variations – an increasingly desired property. This is because for QDI designs only very few timing assumptions and constraints are necessary to guarantee the correct behavior of a circuit, which is in strong contrast to the rigid timing scheme of the traditional synchronous design style. This characteristic key-property opens up many interesting and highly relevant application areas – two of are the focus of this thesis. The inherent robustness against timing variations makes QDI design styles and techniques (i) perfectly suited for constructing delay-insensitive (DI) communication channels for global inter- or intra-chip interconnect and (ii) a promising choice for the design of fault-tolerant systems. The first part of this work is, hence, devoted to the investigation of efficient ways to transmit information in a DI way, as well as the design of interface components that allow the integration of asynchronous circuits in otherwise synchronous systems. We provide a comprehensive analysis of available protocols and data encoding schemes and complement them with our own contributions to the field. The second part, then, explores the fault-tolerance aspects of QDI design. In particular, we analyze the effects of transient faults, investigate fault-mitigation strategies from literature and present and evaluate our own techniques. For that purpose, a comprehensive tool set to generate, analyze and simulate asynchronous circuits has been developed.},
language = {en},
urldate = {2023-05-18},
school = {Technische Universität Wien},
author = {Huemer, Florian Ferdinand},
year = {2022},
doi = {10.34726/hss.2022.107641},
note = {Accepted: 2022-12-09T10:32:19Z},
file = {Huemer Florian Ferdinand - 2022 - Contributions to efficiency and robustness of...pdf:/home/fabian/Zotero/storage/B6678I8B/Huemer Florian Ferdinand - 2022 - Contributions to efficiency and robustness of...pdf:application/pdf},
@article{efraimidisWeightedRandomSampling2006,
title = {Weighted Random Sampling with a Reservoir},
author = {Efraimidis, Pavlos S. and Spirakis, Paul G.},
year = {2006},
month = mar,
journal = {Information Processing Letters},
volume = {97},
number = {5},
pages = {181--185},
issn = {0020-0190},
doi = {10.1016/j.ipl.2005.11.003},
urldate = {2025-01-05},
abstract = {In this work, a new algorithm for drawing a weighted random sample of size m from a population of n weighted items, where m{$\leq$}n, is presented. The algorithm can generate a weighted random sample in one-pass over unknown populations.},
keywords = {Data streams,Parallel algorithms,Randomized algorithms,Reservoir sampling,Weighted random sampling},
file = {/home/fabian/Zotero/storage/RSLCCBUK/Efraimidis and Spirakis - 2006 - Weighted random sampling with a reservoir.pdf;/home/fabian/Zotero/storage/VVPYNCXU/S002001900500298X.html}
}
@article{altera_introduction_2013,
title = {Introduction to {Single}-{Event} {Upsets}},
url = {https://cdrdv2-public.intel.com/650466/wp-01206-introduction-single-event-upsets.pdf},
abstract = {This paper provides an overview of single event upsets (SEU), the capabilities provided in FPGAs to mitigate the effects of SEU, techniques that can be incorporated in user designs to mitigate the effects of SEU, and how tools and intellectual property (IP) can be used to validate a design to ensure high levels of tolerance for SEU.},
journal = {WP-01206-1.0},
author = {Altera},
month = sep,
year = {2013},
file = {Altera_2013_Introduction to Single-Event Upsets.pdf:/home/fabian/Zotero/storage/CDP9CDNW/Altera_2013_Introduction to Single-Event Upsets.pdf:application/pdf},
@article{ferlet-cavroisSingleEventTransients2013,
title = {Single {{Event Transients}} in {{Digital CMOS}}---{{A Review}}},
author = {{Ferlet-Cavrois}, V{\'e}ronique and Massengill, Lloyd W. and Gouker, Pascale},
year = {2013},
month = jun,
journal = {IEEE Transactions on Nuclear Science},
volume = {60},
number = {3},
pages = {1767--1790},
issn = {1558-1578},
doi = {10.1109/TNS.2013.2255624},
urldate = {2025-01-05},
abstract = {The creation of soft errors due to the propagation of single event transients (SETs) is a significant reliability challenge in modern CMOS logic. SET concerns continue to be exacerbated by Moore's Law technology scaling. This paper presents a review of digital single event transient research, including: a brief historical overview of the emergence of SET phenomena, a review of the present understanding of SET mechanisms, a review of the state-of-the-art in SET testing and modelling, a discussion of mitigation techniques, and a discussion of the impact of technology scaling trends on future SET significance.},
keywords = {Clocks,Integrated circuit modeling,Inverters,Logic gates,Single event transients,Transient analysis,Transistors},
file = {/home/fabian/Zotero/storage/QIASCJSK/Ferlet-Cavrois et al. - 2013 - Single Event Transients in Digital CMOS—A Review.pdf;/home/fabian/Zotero/storage/IZWULWWS/6530775.html}
}
@inproceedings{tabassam__2023,
title = {ζ: {A} {Novel} {Approach} for {Mitigating} {Single} {Event} {Transient} {Effects} in {Quasi} {Delay} {Insensitive} {Logic}},
shorttitle = {ζ},
url = {https://ieeexplore.ieee.org/abstract/document/10239589},
doi = {10.1109/ASYNC58294.2023.10239589},
abstract = {Due to their flexible data accepting windows Quasi Delay-Insensitive (QDI) circuits are susceptible to environmental effects such as single event transients (SETs). Their mode of operation often demands that the combinational logic of such circuits contains storage elements in the form of Muller C-element (MCE)s. This fact makes it likely for an SETs to be converted into an single event upset (SEU). Nevertheless, most of the available approaches in literature focus on hardening the butter elements between combinational logic blocks to mitigate the effects of SETs with less emphasis on the logic itself. In this work, we first review existing techniques addressing SETs in combinational logic. We analyze and compare them to a non-resilient basic QDI circuit template. We conclude that these techniques are not effective compared to this basic template because the addition of extra circuitry increases the susceptibility of the overall circuit towards SETs. Some of these techniques are only valid with extra assumptions, one is, exempting the mitigating circuit part from fault injection. Another main limitation is concerning the way in which the circuits flush out faults in the combinational logic. The proposed techniques can easily lead to a violation of the handshake protocol by forcing all combinational signals to zero, which may introduce an additional null phase depending on the next stage. After thorough analysis, we present a technique to flush the erroneous value within the combinational logic while maintaining the remaining part of combinational logic. This flushing does not require extra combinational cycles for re-computing the logic value. We combine our novel flushing approach with a resilient butter style to make the overall circuits highly resilient towards SETs. To facilitate a fair comparison we also utilize this resilient butter template with other combinational logic flushing techniques. For the evaluation of the results, we simulate all techniques with a 16-bit multiplier circuit realized with the NanGate 15nm library. The extensive fault injection experiments show the resilience of our novel combinational logic flushing approach.},
urldate = {2024-12-17},
booktitle = {2023 28th {IEEE} {International} {Symposium} on {Asynchronous} {Circuits} and {Systems} ({ASYNC})},
author = {Tabassam, Zaheer and Steininger, Andreas and Najvirt, Robert and Huemer, Florian},
month = jul,
year = {2023},
note = {ISSN: 2643-1483},
keywords = {Throughput, Protocols, Logic gates, Single event transients, Codes, combinational logic flushing, Dairy products, quasi delay insensitive, single event transients, Single event upsets},
pages = {48--57},
file = {Full Text PDF:/home/fabian/Zotero/storage/7TZVQIIW/Tabassam et al. - 2023 - ζ A Novel Approach for Mitigating Single Event Transient Effects in Quasi Delay Insensitive Logic.pdf:application/pdf;IEEE Xplore Abstract Record:/home/fabian/Zotero/storage/L7XLXJHK/10239589.html:text/html},
@article{heInteractInteractiveDesign,
title = {Interact: {{An Interactive Design Environment}} for {{Asynchronous Logic}}},
author = {He, Jiayuan and Hua, Wenmian and Lu, Yi-Shan and Maleki, Sepideh and Yang, Yihang and Pingali, Keshav and Manohar, Rajit},
abstract = {We are developing an open-source EDA flow for asynchronous logic. We present the current state of the flow, where all the key components have been integrated into a single framework including the timer, partitioner, placer, power detailed router, and global router. We describe enhancements to the flow in terms of the class of circuits that can be handled, and extensions to support third-party libraries and flows.},
langid = {english},
file = {/home/fabian/Zotero/storage/5G9HMT2B/a13.pdf}
}
@phdthesis{schwendinger_evaluation_2022,
type = {Thesis},
title = {Evaluation of different tools for design and fault-injection of asynchronous circuits},
copyright = {http://rightsstatements.org/vocab/InC/1.0/},
url = {https://repositum.tuwien.at/handle/20.500.12708/80366},
abstract = {Asynchronous circuits (ACs) are currently aced out by synchronous circuits (SCs) in industry purposes. Nevertheless there were prominent innovations utilizing ACs in the field of brain-inspired hardware like SpiNNaker, Neurogrid and the TrueNorth. Researchers claim also a theoretical performance advantage of ACs in terms of speed and energy efficiency. However, one handicap when designing ACs is the current lack of tools designated especially to AC design. Often tools originally targeted to SC design are (mis)used. This thesis presents two flows designed especially to AC design. The first one is developed by the Embedded Computing Systems (ECS) group at TU Wien. It is focused on fault-injection experiments at gate level, but provides also Python scripts for high level AC generation. The second one is the Asynchronous Circuit Toolkit (ACT) developed by the asynchronous VLSI and architecture (asyncVLSI) group at YaleUniversity. It aims for a complete coverage of chip design from high level description to fabricable GDSII format. This thesis will extensively present both these flows, and then proceed with their integration into a combined flow. In particular a translation script of the production rule set (PRS) format in its concrete implementation at TU Wien to ACT has been developed. Additionally the fault-injection engine, which is part of the TU Wien flow, has been overhauled to now also support the Prsim simulation software, which is part of the Yale flow. Afterwards, as a proof of concept, for the integrated flow about a million fault-injections have been performed with Modelsim, which was previously without alternative for the TU Wien flow, and Prsim. While one should initially expect the two tools to deliver the same results, mismatches are spotted that could be tracked back to aspects where Modelsim and Prsim operate differently.},
language = {en},
urldate = {2025-01-03},
school = {Technische Universität Wien},
author = {Schwendinger, Martin},
year = {2022},
doi = {10.34726/hss.2022.98624},
note = {Accepted: 2022-09-16T07:23:54Z
Journal Abbreviation: Evaluierung von verschiedenen Tools für Design und Fehlerinjektion von Asynchronen Schaltungen},
file = {Full Text PDF:/home/fabian/Zotero/storage/9EBJ7BI9/Schwendinger - 2022 - Evaluation of different tools for design and fault-injection of asynchronous circuits.pdf:application/pdf},
@phdthesis{huemerContributionsEfficiencyRobustness2022,
type = {Thesis},
title = {Contributions to Efficiency and Robustness of Quasi Delay-Insensitive Circuits},
author = {Huemer, Florian Ferdinand},
year = {2022},
doi = {10.34726/hss.2022.107641},
urldate = {2023-05-18},
abstract = {In the field of digital integrated circuits asynchronous and especially quasi delay-insensitive (QDI) designs are known to have a high robustness against process, voltage and temperature variations -- an increasingly desired property. This is because for QDI designs only very few timing assumptions and constraints are necessary to guarantee the correct behavior of a circuit, which is in strong contrast to the rigid timing scheme of the traditional synchronous design style. This characteristic key-property opens up many interesting and highly relevant application areas -- two of are the focus of this thesis. The inherent robustness against timing variations makes QDI design styles and techniques (i) perfectly suited for constructing delay-insensitive (DI) communication channels for global inter- or intra-chip interconnect and (ii) a promising choice for the design of fault-tolerant systems. The first part of this work is, hence, devoted to the investigation of efficient ways to transmit information in a DI way, as well as the design of interface components that allow the integration of asynchronous circuits in otherwise synchronous systems. We provide a comprehensive analysis of available protocols and data encoding schemes and complement them with our own contributions to the field. The second part, then, explores the fault-tolerance aspects of QDI design. In particular, we analyze the effects of transient faults, investigate fault-mitigation strategies from literature and present and evaluate our own techniques. For that purpose, a comprehensive tool set to generate, analyze and simulate asynchronous circuits has been developed.},
langid = {english},
school = {Technische Universit{\"a}t Wien},
annotation = {Accepted: 2022-12-09T10:32:19Z},
file = {/home/fabian/Zotero/storage/B6678I8B/Huemer Florian Ferdinand - 2022 - Contributions to efficiency and robustness of...pdf}
}
@inproceedings{monnet_asynchronous_2004,
title = {Asynchronous circuits sensitivity to fault injection},
url = {https://ieeexplore.ieee.org/abstract/document/1319669?casa_token=VzWq30-c2KEAAAAA:iDAIQCcGlCTDf9fbAiuJeL0NKzlNQDn8cBCyOK9zdUbdB9XBDNecWy2UTW9j37SJ-xMoMNGjQQ},
doi = {10.1109/OLT.2004.1319669},
abstract = {This paper presents an analysis of the faults sensitivity of Quasi Delay Insensitive (QDI) asynchronous circuits. Faults considered in this work can be either natural or intentional. However, fault injection attacks which consist in causing an intentional temporary dysfunction of a circuit by injecting faults in its combinational or sequential parts are of prime interest. This failure enables hackers to access protected memory areas or secret information like cryptographic keys. This work focuses on analysing the sensitivity of asynchronous circuits to fault injection. A circuit fault-sensitivity criterion is defined, which enables to point out weak parts of the circuits in order to specify hardening strategies.},
urldate = {2025-01-04},
booktitle = {Proceedings. 10th {IEEE} {International} {On}-{Line} {Testing} {Symposium}},
author = {Monnet, Y. and Renaudin, M. and Leveugle, R.},
month = jul,
year = {2004},
keywords = {Delay, Laboratories, Protocols, Circuit faults, Clocks, Asynchronous circuits, Computer hacking, Cryptography, Protection, Smart cards},
pages = {121--126},
file = {Full Text PDF:/home/fabian/Zotero/storage/PQULARRY/Monnet et al. - 2004 - Asynchronous circuits sensitivity to fault injection.pdf:application/pdf;IEEE Xplore Abstract Record:/home/fabian/Zotero/storage/BSZIZQ4S/1319669.html:text/html},
@inproceedings{huemerIdentificationConfinementFault2020,
title = {Identification and {{Confinement}} of {{Fault Sensitivity Windows}} in {{QDI Logic}}},
booktitle = {2020 {{Austrochip Workshop}} on {{Microelectronics}} ({{Austrochip}})},
author = {Huemer, Florian and Najvirt, Robert and Steininger, Andreas},
year = {2020},
month = oct,
pages = {29--36},
doi = {10.1109/Austrochip51129.2020.9232985},
abstract = {Asynchronous, specifically QDI circuits are known to exhibit high resilience against faults affecting the timing. At the same time, their event based operation principle makes them susceptible to glitches. While synchronous circuits obtain high resilience through temporal masking that is established through the sampling of data by flip flops, asynchronous designs, by trying to be flexible about the phases of data validity, often have lower masking capabilities. Consequently, previous work has proposed to narrow down the windows in which data changes are accepted, in order to improve the temporal masking in QDI designs.In this paper we study the natural resilience of different QDI templates in more detail and quantitatively determine the windows of vulnerability through extensive fault injection experiments in simulation. To this end we propose a novel way of visualizing and analyzing the sensitivity windows that aids in identifying the key dependencies and vulnerabilities. In addition we introduce and evaluate two low-cost extensions for the pipeline registers which allow either to stall the operation in case a glitch creates an illegal symbol, or to prevent the creation of an illegal symbol in the first place.},
keywords = {Circuit faults,Integrated circuit modeling,Logic gates,Pipelines,Protocols,Rails,Resilience},
file = {/home/fabian/Zotero/storage/HEG9QF34/Huemer et al_2020_Identification and Confinement of Fault Sensitivity Windows in QDI Logic.pdf;/home/fabian/Zotero/storage/RJLXL75V/Huemer et al. - 2020 - Identification and Confinement of Fault Sensitivit.pdf;/home/fabian/Zotero/storage/IQUBBXXK/9232985.html}
}
@inproceedings{bainbridge_glitch_2009,
title = {Glitch {Sensitivity} and {Defense} of {Quasi} {Delay}-{Insensitive} {Network}-on-{Chip} {Links}},
url = {https://ieeexplore.ieee.org/abstract/document/5010334},
doi = {10.1109/ASYNC.2009.18},
abstract = {To the casual observer, glitches occurring in quasi delay-insensitive logic would appear to cause incorrect operation and render the circuits unusable. This paper presents an informal analysis of the effects of glitches occurring on the long interconnect wires connecting logical units of a network-on-chip (NoC) using quasi delay-insensitive (QDI) techniques. This is followed by the introduction and analysis of a set of techniques to reduce the likelihood and impact of such hazards affecting the circuit. Post layout area and performance impacts are presented for a 90 nm process.},
urldate = {2025-01-04},
booktitle = {2009 15th {IEEE} {Symposium} on {Asynchronous} {Circuits} and {Systems}},
author = {Bainbridge, William John and Salisbury, Sean James},
month = may,
year = {2009},
note = {ISSN: 1522-8681},
keywords = {Pipelines, Asynchronous circuits, QDI, Asynchronous, Delay effects, Delay Insensitive, Electromagnetic coupling, Electromagnetic interference, Glitch, Hazard, Hazards, Integrated circuit interconnections, Logic circuits, Network-on-a-chip, Network-on-Chip, NoC, Wires},
pages = {35--44},
file = {Full Text PDF:/home/fabian/Zotero/storage/S63EJBW8/Bainbridge and Salisbury - 2009 - Glitch Sensitivity and Defense of Quasi Delay-Insensitive Network-on-Chip Links.pdf:application/pdf;IEEE Xplore Abstract Record:/home/fabian/Zotero/storage/CT84FYAU/5010334.html:text/html},
@inproceedings{jangSEUtolerantQDICircuits2005,
title = {{{SEU-tolerant QDI}} Circuits [Quasi Delay-Insensitive Asynchronous Circuits]},
booktitle = {11th {{IEEE International Symposium}} on {{Asynchronous Circuits}} and {{Systems}}},
author = {Jang, Wonjin and Martin, A.J.},
year = {2005},
month = mar,
pages = {156--165},
issn = {1522-8681},
doi = {10.1109/ASYNC.2005.30},
urldate = {2025-01-04},
abstract = {This paper addresses the issue of single-event upset (SEU) in quasi delay-insensitive (QDI) asynchronous circuits. We show that an SEU can cause abnormal computations in QDI circuits beside deadlock, and we propose a general method to make QDI circuits SEU-tolerant. We present simplified SEU-tolerant buffer implementations for CMOS technology. Finally, we present a case study of a one-bit comparator and show SPICE-simulation results.},
keywords = {Circuits},
file = {/home/fabian/Zotero/storage/2UE6RWYF/Jang and Martin - 2005 - SEU-tolerant QDI circuits [quasi delay-insensitive asynchronous circuits].pdf;/home/fabian/Zotero/storage/2FJ74JFH/1402057.html}
}
@inproceedings{jang_seu-tolerant_2005,
title = {{SEU}-tolerant {QDI} circuits [quasi delay-insensitive asynchronous circuits]},
url = {https://ieeexplore.ieee.org/abstract/document/1402057},
doi = {10.1109/ASYNC.2005.30},
abstract = {This paper addresses the issue of single-event upset (SEU) in quasi delay-insensitive (QDI) asynchronous circuits. We show that an SEU can cause abnormal computations in QDI circuits beside deadlock, and we propose a general method to make QDI circuits SEU-tolerant. We present simplified SEU-tolerant buffer implementations for CMOS technology. Finally, we present a case study of a one-bit comparator and show SPICE-simulation results.},
urldate = {2025-01-04},
booktitle = {11th {IEEE} {International} {Symposium} on {Asynchronous} {Circuits} and {Systems}},
author = {Jang, Wonjin and Martin, A.J.},
month = mar,
year = {2005},
note = {ISSN: 1522-8681},
keywords = {Circuits},
pages = {156--165},
file = {Full Text PDF:/home/fabian/Zotero/storage/2UE6RWYF/Jang and Martin - 2005 - SEU-tolerant QDI circuits [quasi delay-insensitive asynchronous circuits].pdf:application/pdf;IEEE Xplore Abstract Record:/home/fabian/Zotero/storage/2FJ74JFH/1402057.html:text/html},
@techreport{manoharOpenSourceDesign,
title = {An {{Open Source Design Flow}} for {{Asynchronous Circuits}}},
author = {Manohar, Rajit},
year = {2019},
urldate = {2023-03-22},
abstract = {There have been a number of small-scale and large-scale technology demonstrations of asynchronous circuits, showing that they have benefits in performance and power efficiency in a variety of application domains. Most recently, asynchronous circuits were used in the TrueNorth neuromorphic chip to achieve unprecedented energy-efficiency for neuromorphic systems. However, these circuits cannot be easily adopted, because commercially available design tools do not support asynchronous logic. As part of the DARPA ERI effort, we are addressing this challenge by developing a set of open-source design tools for asynchronous circuits.},
chapter = {Technical Reports},
langid = {english},
file = {/home/fabian/Zotero/storage/V3WLFW8A/Manohar - An Open-Source Design Flow for Asynchronous Circui.pdf}
}
@inproceedings{mcgee_level-encoded_2008,
title = {A {Level}-{Encoded} {Transition} {Signaling} {Protocol} for {High}-{Throughput} {Asynchronous} {Global} {Communication}},
url = {https://ieeexplore.ieee.org/abstract/document/4557004},
doi = {10.1109/ASYNC.2008.24},
abstract = {A new delay-insensitive data encoding scheme for global communication, level-encoded transition signaling (LETS), is introduced. LETS is a generalization of level-encoded dual rail (LEDR), an earlier non-return-to-zero encoding scheme where one of two wires changes value per data bit per transaction. In LETS, only one of N = 2n (1-of-N) wire changes value per n data bits per transaction. Compared to most common return-to-zero encoding schemes, LETS has potential power and throughput advantages, since fewer rails switch and no return-to-zero phase is required. Compared to existing nonreturn-to-zero schemes (i.e., LEDR), higher-dimension LETS codes have a potential power advantage, with significantly reduced switching activity per data bit.Two alternative 1-of-4 LETS codes are proposed, and efficient hardware for completion detection and conversion to return-to-zero protocols is introduced. Finally, a general theoretical framework is presented which characterizes the properties of arbitrary 1-of-N LETS codes, as well as a simple procedure to generate such codes.},
urldate = {2025-01-04},
booktitle = {2008 14th {IEEE} {International} {Symposium} on {Asynchronous} {Circuits} and {Systems}},
author = {McGee, Peggy B. and Agyekum, Melinda Y. and Mohamed, Moustafa A. and Nowick, Steven M.},
month = apr,
year = {2008},
note = {ISSN: 1522-8681},
keywords = {Throughput, Hardware, Character generation, Delay, Switches, Encoding, Protocols, Rails, Wires, Global communication},
pages = {116--127},
file = {Full Text PDF:/home/fabian/Zotero/storage/6ACGIVSX/McGee et al. - 2008 - A Level-Encoded Transition Signaling Protocol for High-Throughput Asynchronous Global Communication.pdf:application/pdf;IEEE Xplore Abstract Record:/home/fabian/Zotero/storage/U73E7C33/4557004.html:text/html},
@inproceedings{mcgeeLevelEncodedTransitionSignaling2008,
title = {A {{Level-Encoded Transition Signaling Protocol}} for {{High-Throughput Asynchronous Global Communication}}},
booktitle = {2008 14th {{IEEE International Symposium}} on {{Asynchronous Circuits}} and {{Systems}}},
author = {McGee, Peggy B. and Agyekum, Melinda Y. and Mohamed, Moustafa A. and Nowick, Steven M.},
year = {2008},
month = apr,
pages = {116--127},
issn = {1522-8681},
doi = {10.1109/ASYNC.2008.24},
urldate = {2025-01-04},
abstract = {A new delay-insensitive data encoding scheme for global communication, level-encoded transition signaling (LETS), is introduced. LETS is a generalization of level-encoded dual rail (LEDR), an earlier non-return-to-zero encoding scheme where one of two wires changes value per data bit per transaction. In LETS, only one of N = 2n (1-of-N) wire changes value per n data bits per transaction. Compared to most common return-to-zero encoding schemes, LETS has potential power and throughput advantages, since fewer rails switch and no return-to-zero phase is required. Compared to existing nonreturn-to-zero schemes (i.e., LEDR), higher-dimension LETS codes have a potential power advantage, with significantly reduced switching activity per data bit.Two alternative 1-of-4 LETS codes are proposed, and efficient hardware for completion detection and conversion to return-to-zero protocols is introduced. Finally, a general theoretical framework is presented which characterizes the properties of arbitrary 1-of-N LETS codes, as well as a simple procedure to generate such codes.},
keywords = {Character generation,Delay,Encoding,Global communication,Hardware,Protocols,Rails,Switches,Throughput,Wires},
file = {/home/fabian/Zotero/storage/6ACGIVSX/McGee et al. - 2008 - A Level-Encoded Transition Signaling Protocol for High-Throughput Asynchronous Global Communication.pdf;/home/fabian/Zotero/storage/U73E7C33/4557004.html}
}
@inproceedings{vezzoli_designing_2024,
title = {Designing an {Energy}-{Efficient} {Fully}-{Asynchronous} {Deep} {Learning} {Convolution} {Engine}},
url = {https://ieeexplore.ieee.org/abstract/document/10546579?casa_token=oOEtwQgdhy0AAAAA:qgIlHzgpaATvA0I_s_f17d7l-Y4_hs-yesK6eY4Yg0Fa-M0dh7N0YqtFDsY0gNYQ934XrzYIgg},
doi = {10.23919/DATE58400.2024.10546579},
abstract = {In the face of exponential growth in semiconductor energy usage, there is a significant push towards highly energy-efficient microelectronics design. While the traditional circuit designs typically employ clocks to synchronize the computing operations, these circuits incur significant performance and energy overheads due to their data-independent worst-case operation and complex clock tree networks. In this paper, we explore asynchronous or clockless techniques where clocks are replaced by request, acknowledge handshaking signals. To quantify the potential energy and performance gains of asynchronous logic, we design a highly energy -efficient asynchronous deep learning convolution engine, which uses 87 \% of total DL accelerator energy. Our asynchronous design shows 5.06x lower energy and 5.09 x lower delay than the synchronous one.},
urldate = {2025-01-04},
booktitle = {2024 {Design}, {Automation} \& {Test} in {Europe} {Conference} \& {Exhibition} ({DATE})},
author = {Vezzoli, Mattia and Nel, Lukas and Bhardwaj, Kshitij and Manohar, Rajit and Gokhale, Maya},
month = mar,
year = {2024},
note = {ISSN: 1558-1101},
keywords = {Protocols, Deep learning, Energy efficiency, Microelectronics, Convolution, Performance gain, Potential energy},
pages = {1--2},
file = {Full Text PDF:/home/fabian/Zotero/storage/ZJYHV4YF/Vezzoli et al. - 2024 - Designing an Energy-Efficient Fully-Asynchronous Deep Learning Convolution Engine.pdf:application/pdf;IEEE Xplore Abstract Record:/home/fabian/Zotero/storage/MLL9B696/10546579.html:text/html},
@inproceedings{monnetAsynchronousCircuitsSensitivity2004,
title = {Asynchronous Circuits Sensitivity to Fault Injection},
booktitle = {Proceedings. 10th {{IEEE International On-Line Testing Symposium}}},
author = {Monnet, Y. and Renaudin, M. and Leveugle, R.},
year = {2004},
month = jul,
pages = {121--126},
doi = {10.1109/OLT.2004.1319669},
urldate = {2025-01-04},
abstract = {This paper presents an analysis of the faults sensitivity of Quasi Delay Insensitive (QDI) asynchronous circuits. Faults considered in this work can be either natural or intentional. However, fault injection attacks which consist in causing an intentional temporary dysfunction of a circuit by injecting faults in its combinational or sequential parts are of prime interest. This failure enables hackers to access protected memory areas or secret information like cryptographic keys. This work focuses on analysing the sensitivity of asynchronous circuits to fault injection. A circuit fault-sensitivity criterion is defined, which enables to point out weak parts of the circuits in order to specify hardening strategies.},
keywords = {Asynchronous circuits,Circuit faults,Clocks,Computer hacking,Cryptography,Delay,Laboratories,Protection,Protocols,Smart cards},
file = {/home/fabian/Zotero/storage/PQULARRY/Monnet et al. - 2004 - Asynchronous circuits sensitivity to fault injection.pdf;/home/fabian/Zotero/storage/BSZIZQ4S/1319669.html}
}
@article{he_interact_nodate,
title = {interact: {An} {Interactive} {Design} {Environment} for {Asynchronous} {Logic}},
abstract = {We are developing an open-source EDA flow for asynchronous logic. We present the current state of the flow, where all the key components have been integrated into a single framework including the timer, partitioner, placer, power detailed router, and global router. We describe enhancements to the flow in terms of the class of circuits that can be handled, and extensions to support third-party libraries and flows.},
language = {en},
author = {He, Jiayuan and Hua, Wenmian and Lu, Yi-Shan and Maleki, Sepideh and Yang, Yihang and Pingali, Keshav and Manohar, Rajit},
file = {a13.pdf:/home/fabian/Zotero/storage/5G9HMT2B/a13.pdf:application/pdf},
@article{nelsonFaulttolerantComputingFundamental1990,
title = {Fault-Tolerant Computing: Fundamental Concepts},
shorttitle = {Fault-Tolerant Computing},
author = {Nelson, V.P.},
year = {1990},
month = jul,
journal = {Computer},
volume = {23},
number = {7},
pages = {19--25},
issn = {1558-0814},
doi = {10.1109/2.56849},
urldate = {2025-01-05},
abstract = {The basic concepts of fault-tolerant computing are reviewed, focusing on hardware. Failures, faults, and errors in digital systems are examined, and measures of dependability, which dictate and evaluate fault-tolerance strategies for different classes of applications, are defined. The elements of fault-tolerance strategies are identified, and various strategies are reviewed. They are: error detection, masking, and correction; error detection and correction codes; self-checking logic; module replication for error detection and masking; protocol and timing checks; fault containment; reconfiguration and repair; and system recovery.{$<>$}},
keywords = {Digital systems,Error correction codes,Fault detection,Fault diagnosis,Fault tolerance,Fault tolerant systems,Hardware,Protocols,Reconfigurable logic,Timing},
file = {/home/fabian/Zotero/storage/YK87FIE6/Nelson - 1990 - Fault-tolerant computing fundamental concepts.pdf;/home/fabian/Zotero/storage/6L9B3B2P/56849.html}
}
@phdthesis{schwendingerEvaluationDifferentTools2022a,
type = {Thesis},
title = {Evaluation of Different Tools for Design and Fault-Injection of Asynchronous Circuits},
author = {Schwendinger, Martin},
year = {2022},
doi = {10.34726/hss.2022.98624},
urldate = {2025-01-03},
abstract = {Asynchronous circuits (ACs) are currently aced out by synchronous circuits (SCs) in industry purposes. Nevertheless there were prominent innovations utilizing ACs in the field of brain-inspired hardware like SpiNNaker, Neurogrid and the TrueNorth. Researchers claim also a theoretical performance advantage of ACs in terms of speed and energy efficiency. However, one handicap when designing ACs is the current lack of tools designated especially to AC design. Often tools originally targeted to SC design are (mis)used. This thesis presents two flows designed especially to AC design. The first one is developed by the Embedded Computing Systems (ECS) group at TU Wien. It is focused on fault-injection experiments at gate level, but provides also Python scripts for high level AC generation. The second one is the Asynchronous Circuit Toolkit (ACT) developed by the asynchronous VLSI and architecture (asyncVLSI) group at YaleUniversity. It aims for a complete coverage of chip design from high level description to fabricable GDSII format. This thesis will extensively present both these flows, and then proceed with their integration into a combined flow. In particular a translation script of the production rule set (PRS) format in its concrete implementation at TU Wien to ACT has been developed. Additionally the fault-injection engine, which is part of the TU Wien flow, has been overhauled to now also support the Prsim simulation software, which is part of the Yale flow. Afterwards, as a proof of concept, for the integrated flow about a million fault-injections have been performed with Modelsim, which was previously without alternative for the TU Wien flow, and Prsim. While one should initially expect the two tools to deliver the same results, mismatches are spotted that could be tracked back to aspects where Modelsim and Prsim operate differently.},
copyright = {http://rightsstatements.org/vocab/InC/1.0/},
langid = {english},
school = {Technische Universit{\"a}t Wien},
annotation = {Accepted: 2022-09-16T07:23:54Z},
file = {/home/fabian/Zotero/storage/9EBJ7BI9/Schwendinger - 2022 - Evaluation of different tools for design and fault-injection of asynchronous circuits.pdf}
}
@inproceedings{tabassamNovelApproachMitigating2023,
title = {{$\zeta$}: {{A Novel Approach}} for {{Mitigating Single Event Transient Effects}} in {{Quasi Delay Insensitive Logic}}},
shorttitle = {{$\zeta$}},
booktitle = {2023 28th {{IEEE International Symposium}} on {{Asynchronous Circuits}} and {{Systems}} ({{ASYNC}})},
author = {Tabassam, Zaheer and Steininger, Andreas and Najvirt, Robert and Huemer, Florian},
year = {2023},
month = jul,
pages = {48--57},
issn = {2643-1483},
doi = {10.1109/ASYNC58294.2023.10239589},
urldate = {2024-12-17},
abstract = {Due to their flexible data accepting windows Quasi Delay-Insensitive (QDI) circuits are susceptible to environmental effects such as single event transients (SETs). Their mode of operation often demands that the combinational logic of such circuits contains storage elements in the form of Muller C-element (MCE)s. This fact makes it likely for an SETs to be converted into an single event upset (SEU). Nevertheless, most of the available approaches in literature focus on hardening the butter elements between combinational logic blocks to mitigate the effects of SETs with less emphasis on the logic itself. In this work, we first review existing techniques addressing SETs in combinational logic. We analyze and compare them to a non-resilient basic QDI circuit template. We conclude that these techniques are not effective compared to this basic template because the addition of extra circuitry increases the susceptibility of the overall circuit towards SETs. Some of these techniques are only valid with extra assumptions, one is, exempting the mitigating circuit part from fault injection. Another main limitation is concerning the way in which the circuits flush out faults in the combinational logic. The proposed techniques can easily lead to a violation of the handshake protocol by forcing all combinational signals to zero, which may introduce an additional null phase depending on the next stage. After thorough analysis, we present a technique to flush the erroneous value within the combinational logic while maintaining the remaining part of combinational logic. This flushing does not require extra combinational cycles for re-computing the logic value. We combine our novel flushing approach with a resilient butter style to make the overall circuits highly resilient towards SETs. To facilitate a fair comparison we also utilize this resilient butter template with other combinational logic flushing techniques. For the evaluation of the results, we simulate all techniques with a 16-bit multiplier circuit realized with the NanGate 15nm library. The extensive fault injection experiments show the resilience of our novel combinational logic flushing approach.},
keywords = {Codes,combinational logic flushing,Dairy products,Logic gates,Protocols,quasi delay insensitive,single event transients,Single event transients,Single event upsets,Throughput},
file = {/home/fabian/Zotero/storage/7TZVQIIW/Tabassam et al. - 2023 - ζ A Novel Approach for Mitigating Single Event Transient Effects in Quasi Delay Insensitive Logic.pdf;/home/fabian/Zotero/storage/L7XLXJHK/10239589.html}
}
@inproceedings{vezzoliDesigningEnergyEfficientFullyAsynchronous2024,
title = {Designing an {{Energy-Efficient Fully-Asynchronous Deep Learning Convolution Engine}}},
booktitle = {2024 {{Design}}, {{Automation}} \& {{Test}} in {{Europe Conference}} \& {{Exhibition}} ({{DATE}})},
author = {Vezzoli, Mattia and Nel, Lukas and Bhardwaj, Kshitij and Manohar, Rajit and Gokhale, Maya},
year = {2024},
month = mar,
pages = {1--2},
issn = {1558-1101},
doi = {10.23919/DATE58400.2024.10546579},
urldate = {2025-01-04},
abstract = {In the face of exponential growth in semiconductor energy usage, there is a significant push towards highly energy-efficient microelectronics design. While the traditional circuit designs typically employ clocks to synchronize the computing operations, these circuits incur significant performance and energy overheads due to their data-independent worst-case operation and complex clock tree networks. In this paper, we explore asynchronous or clockless techniques where clocks are replaced by request, acknowledge handshaking signals. To quantify the potential energy and performance gains of asynchronous logic, we design a highly energy -efficient asynchronous deep learning convolution engine, which uses 87 \% of total DL accelerator energy. Our asynchronous design shows 5.06x lower energy and 5.09 x lower delay than the synchronous one.},
keywords = {Convolution,Deep learning,Energy efficiency,Microelectronics,Performance gain,Potential energy,Protocols},
file = {/home/fabian/Zotero/storage/ZJYHV4YF/Vezzoli et al. - 2024 - Designing an Energy-Efficient Fully-Asynchronous Deep Learning Convolution Engine.pdf;/home/fabian/Zotero/storage/MLL9B696/10546579.html}
}
@book{von1939aufteilungs,
title = {{\"U}ber Aufteilungs-Und Besetzungswahrscheinlichkeiten},
author = {Von Mises, Richard},
year = {1939},
publisher = {na}
}

137
fault_injection_async25.tex
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@ -11,6 +11,14 @@
\usepackage{xcolor}
\usepackage{orcidlink}
\usepackage[shortcuts,acronym]{glossaries}
\usepackage{subcaption}
% Tikz because graphs are fun
\usepackage{tikz}
\usepackage{tikz-timing}
\usepackage{tikz-timing-overlays}
\usepackage{tikz-timing-advnodes}
\usetikzlibrary{positioning}
\makeglossaries
% Acronyms for the document
@ -19,9 +27,12 @@
\newacronym{wchb}{WCHB}{Weakly Conditioned Half Buffer}
\newacronym{qdi}{QDI}{Quasi Delay Insensitive}
\newacronym{set}{SET}{Single Event Transient}
\newacronym{seu}{SEU}{Single Event Upset}
\newacronym{prs}{PRS}{Production Rule Set}
% Simple citation required command
\newcommand{\citationneeded}{\textcolor{red}{[citation needed]}}
\newcommand{\referenceneeded}{\textcolor{red}{[reference needed]}}
\def\BibTeX{{\rm B\kern-.05em{\sc i\kern-.025em b}\kern-.08em
T\kern-.1667em\lower.7ex\hbox{E}\kern-.125emX}}
@ -75,91 +86,106 @@ asynchronous circuits, SET, fault-tolerance, cluster computing, computer aided d
\section{Introduction}
To make new things, we require tools. But while commercial tools offer access to the current state of the industry, they are usually not customizable enough (as they tend to be closed source) or - for more specialized applications - not available altogether. This problem is well understood for asynchronous logic, as the commercial offerings' focus on synchronous designs limits functionality for everything outside their scope. And while many of these problems have been mitigated by the publication of the open source ACT toolchain by the Yale AVLSI group \cite{manohar_open_2019}, local compute often does not suffice for tasks that are more complex.
To make new things, we require tools. But while commercial tools offer access to the current state of the industry, they are usually not customizable enough (as they tend to be closed source) or - for more specialized applications - not available altogether. This problem is well understood for asynchronous logic, as the commercial offerings' focus on synchronous designs limits functionality for everything outside their scope. And while many of these problems have been mitigated by the publication of the open source ACT toolchain by the Yale AVLSI group \cite{manoharOpenSourceDesign}, local compute often does not suffice for tasks that are more complex.
Especially for those that lend themselves nicely to a high degree of parallelization, cluster computing offers high potential speed improvements. For this reason, we have built a tool which does just that - while offering a simple \acs{api} to vastly extend its functionality. Our goal was to create a framework to build on, and we here present a real world use-case to demonstrate this capability.
Exposing digital circuits to environments like space can break some of the most basic assumptions we make when designing digital circuits. Given the level of miniaturization we have access to, having high energy particles rain upon the millions of interconnects in an average design can introduce unexpected behavior. These undesired deviations from design specification, or \emph{failures}, need to be well understood to make predictions about a design's robustness.
Synchronizing logic to a clock cycle, while potentially compromising on average case performance, has the helpful side-effect of creating a temporal mask for logic faults. This means that when an erroneous value is induced in a wire, only a small window of time exists where this value can propagate beyond the next logic buffer. \\
In asynchronous logic, we unfortunately lack this convenient abstraction. While we assume temporal masking to also play a much less obvious role in asynchronous logic \cite{huemer_identification_2020}, environmentally induced faults are still a much higher potential risk compared to a clock synchronized design.
In asynchronous logic, we unfortunately lack this convenient abstraction. While we assume temporal masking to also play a much less obvious role in asynchronous logic \cite{huemerIdentificationConfinementFault2020}, environmentally induced faults are still a much higher potential risk compared to a clock synchronized design.
But what is often much more important than knowing \emph{if} a design can fail under certain (extreme) circumstances, is \emph{how} exactly these failure modes play out. Certain use-cases might call for or even enforce safety in form of known failure modes on critical systems. While multiple attempts have been made to create tooling for exploration of fault-space in the past \cite{behal_towards_2021}, as of yet these tools have several shortcomings, which we feel need to be addressed.
But what is often much more important than knowing \emph{if} a design can fail under certain (extreme) circumstances, is \emph{how} exactly these failure modes play out. Certain use-cases might call for or even enforce safety in form of known failure modes on critical systems. While multiple attempts have been made to create tooling for exploration of fault-space in the past \cite{behalExplainingFaultSensitivity2021}, as of yet these tools have several shortcomings, which we feel need to be addressed.
\section{Related Work}
\texttt{action} is an addition to the ACT toolchain initially presented in \cite{manohar_open_2019}. ACT aims to be a collection of tools for an end-to-end chip design workflow. While the main focus of its tools is asynchronous designs, it is powerful enough to also map to synchronous logic families without issue \cite{vezzoli_designing_2024}. The current version of the ACT toolflow does include a scripting environment \cite{he_interact_nodate}, it does however not contain a solution for distributed computing tasks, which would be helpful for testing and verification tasks.
\texttt{action} is an addition to the ACT toolchain initially presented in \cite{manoharOpenSourceDesign}. ACT aims to be a collection of tools for an end-to-end chip design workflow. While the main focus of its tools is asynchronous designs, it is powerful enough to also map to synchronous logic families without issue \cite{vezzoliDesigningEnergyEfficientFullyAsynchronous2024}. The current version of the ACT toolflow does include a scripting environment \cite{heInteractInteractiveDesign}, it does however not contain a solution for distributed computing tasks, which would be helpful for testing and verification tasks.
Focusing on our specific demo use-case, the tool presented in \cite{behal_towards_2021} is a fault injection and fault space exploration tool, aiming to explore fault types in a given circuit. It is quite similar to the demo use-case we show in this paper. It distinguishes fault classes \emph{timing deviation}, \emph{value fault}, \emph{code fault}, \emph{glitch}, \emph{deadlock}, and \emph{token count error}, which are largely reused for this paper (more on our system model in Section \ref{sec:system_model}). The core simulator used is QuestaSim (version 10.6c), which is a commercial simulation tool. To reduce the runtime of one simulation, a cluster based approach is employed to parallelize simulations over multiple machines. This tool has been designed for the \texttt{pypr} toolchain designed by the Huemer at TU Wien \cite{huemer_contributions_2022}, a production rule based circuit description framework in Python. Notably, the system calculates the number of required injections using a system of average injection density, independently of which signal it is targeting. This is one of the main points on which we will try to improve upon.\\
Focusing on our specific demo use-case, the tool presented in \cite{behalExplainingFaultSensitivity2021} is a fault injection and fault space exploration tool, aiming to explore fault types in a given circuit. It is quite similar to the demo use-case we show in this paper. It distinguishes fault classes \emph{timing deviation}, \emph{value fault}, \emph{code fault}, \emph{glitch}, \emph{deadlock}, and \emph{token count error}, which are largely reused for this paper (more on our system model in Section \ref{sec:system_model/failures}). The core simulator used is QuestaSim (version 10.6c), which is a commercial simulation tool. To reduce the runtime of one simulation, a cluster based approach is employed to parallelize simulations over multiple machines. This tool has been designed for the \texttt{pypr} toolchain designed by the Huemer at TU Wien \cite{huemerContributionsEfficiencyRobustness2022}, a production rule based circuit description framework in Python. Notably, the system calculates the number of required injections using a system of average injection density, independently of which signal it is targeting. This is one of the main points on which we will try to improve upon.\\
% should i include work in master thesis?
An iteration of this system can be found in \cite{schwendinger_evaluation_2022}. While based on the same core toolflow, Behal adds limited bridging logic to the ACT toolchain, using \textrm{prsim} \cite{manohar_open_2019} as an alternative simulator. This change requires low level simulation of additional logic, as certain required features were not supported by \texttt{prsim} and no extension to the core simulator code was written. This again is a major point for potential improvement.
An iteration of this system can be found in \cite{schwendingerEvaluationDifferentTools2022a}. While based on the same core toolflow, Behal adds limited bridging logic to the ACT toolchain, using \textrm{prsim} \cite{manoharOpenSourceDesign} as an alternative simulator. This change requires low level simulation of additional logic, as certain required features were not supported by \texttt{prsim} and no extension to the core simulator code was written. This again is a major point for potential improvement.
Finally, we want to briefly touch on different fault-mitigation techniques seen in literature. \\
Bainbridge and Salisbury \cite{bainbridge_glitch_2009} talks about the basic possibilities for fault behavior in \ac{qdi} circuits. Much like \cite{behal_towards_2021}, it identifies specific scenarios which can occur when a \ac{set} is injected into a circuit. We will come back to this in Section \ref{sec:system_model} as well. It then lays out basic mitigation techniques, which largely focus on either introducing some form of redundancy in the circuit or reducing the temporal size of the window in which faults are converted into failure behavior (sensitivity window).
Bainbridge and Salisbury \cite{bainbridgeGlitchSensitivityDefense2009} talks about the basic possibilities for fault behavior in \ac{qdi} circuits. Much like \cite{behalExplainingFaultSensitivity2021}, it identifies specific scenarios which can occur when a \ac{set} is injected into a circuit. We will come back to this in Section \ref{sec:system_model/failures} as well. It then lays out basic mitigation techniques, which largely focus on either introducing some form of redundancy in the circuit or reducing the temporal size of the window in which faults are converted into failure behavior (sensitivity window).
In a similar fashion, Huemer et.al \cite{huemer_identification_2020} presents interlocking and deadlocking versions of a \ac{wchb}. These are also meant to reduce the sensitivity window size, as well as preventing the propagation of illegal symbols. We will use their implementations for interlocking and deadlocking \acp{wchb} in this paper (more in Section \ref{sec:experiment_setup}).
In a similar fashion, Huemer et.al \cite{huemerIdentificationConfinementFault2020} presents interlocking and deadlocking versions of a \ac{wchb}. These are also meant to reduce the sensitivity window size, as well as preventing the propagation of illegal symbols. We will use their implementations for interlocking and deadlocking \acp{wchb} in this paper (more in Section \ref{sec:experiment_setup}).
\section{System Model}
\label{sec:system_model}
\subsection{On fault nomenclature}
It is important to note the fundamental difference between fault and failure in this context. A failure is the inability of a system to perform its specified task. Failures are caused by faults in the system, which can stem from design errors as well as external conditions \cite{nelsonFaulttolerantComputingFundamental1990}. For this paper we will only consider faults caused by external factors as suppose to internal design faults.
Points to talk about
\subsection{Fault model}
\label{sec:system_model/faults}
This work mainly focused on the effects of \acfp{set}, where a wire is manually forced to a specific value, independently of what value the design would dictate. These transient effects can occur due to physical effects like ionizing radiation exposure or electromagnetic interference. After the \ac{set} ends, the wire returns to normal operation. This is an important distinction to a \acf{seu}, where a faulty value is latched by a memory cell. An \ac{set} can but does not necessary lead to an \ac{seu}.
\begin{figure}
\centering
\begin{subfigure}{0.4\textwidth}
\begin{center}
\scalebox{0.85}{\input{graphics/tri_fork_possible.tex}}
\end{center}
\caption{Node with 3-fork, only one leaf receives the transient}
\label{fig:model/3_fork_possible}
\end{subfigure}
\bigskip
\begin{subfigure}{0.4\textwidth}
\begin{center}
\scalebox{0.85}{\input{graphics/tri_fork_impossible.tex}}
\end{center}
\caption{Node with 3-fork, two leafs receive the transient}
\label{fig:model/3_fork_impossible}
\end{subfigure}
\caption{Fanout configurations of nodes and representation in model}
\label{fig:model/forks}
\end{figure}
We simulate our \ac{dut} on the \ac{prs} level. In the simulator, one \ac{prs} node consists of a pull-up, a pull-down, weak pull-up, and weak pull-down stack resulting in one output value. When an \ac{set} is injected, this output value is manually overridden; such an override does however not necessarily incur an output value change. If an \ac{set} is injected into a node, the output value of the node must be different to the forced value for the \ac{set} to be visible at the output. For an \ac{set} to propagate, the child nodes of the victim must be activated on their respective input - meaning a change of the targeted parent would also change their value. Since we attack only one output per simulation, we can only represent scenarios where, given a fanout-tree free of non-sensitive children, one node expresses an incorrect value output. A visual representation of these limitations is shown in Figure \ref{fig:model/forks}, where Subfigure \ref{fig:model/3_fork_possible} can be simulated in our model, while Subfigure \ref{fig:model/3_fork_impossible} cannot.
We feel comfortable with this limitation, as transients usually occur in either the junctions of a given gate, or a transmission wire \cite{ferlet-cavroisSingleEventTransients2013}, which leads to fault behavior similar to what our model can produce.
\subsection{Failure model}
\label{sec:system_model/failures}
When a transient is injected into a node, and given it is not masked by either the current state of the wire or by the child not being inside a sensitivity window currently, we can differentiate between
\begin{itemize}
\item different types of faults that can occur
\item upset vs transient
\item single event delay (if we want to throw that in)
\item Nothing; the glitch is masked either by the target already being and organically staying at the forced value for the duration of the glitch.
\item The node is already at the forced value but would naturally transition during the glitch; the circuit experiences a temporary slowdown but should be able to resume normal operation afterwards. We classify this as a \emph{timing failure} (or a potential \emph{value failure} in non-DI logic families)
\item The glitch removes the spacing between value tokens and one is lost; this would manifest in a \emph{token count failure} (and potentially a \emph{value failure})
\item The glitch acts as additional spacing between what is perceived as two data tokens, injecting an additional one into the pipeline. This would also result in a \emph{token count failure} (and potentially a \emph{value failure})
\item The glitch changes the value of a data line and thus creates a \emph{value failure} or, in a DI-coding, a potential \emph{coding failure}
\item A non-recoverable state is reached in the circuit, resulting in a \emph{deadlock}
\end{itemize}
Talk about fault outcomes in \cite{bainbridge_glitch_2009}
\subsection{Per-Node Fault Space}
Points to talk about
\begin{itemize}
\item fault is injected as output from one node diverges from specification
\item show why this makes sense: only certain input combinations would activate a gate in a way where it could create erroneous output; everything else is logically masked $\rightarrow$ simulation doesn't make sense anyway
\item which fault scenarios can and cannot be simulated
\item show some graphs for this
\end{itemize}
First, these tools should be natively part of the toolchain slowly emerging as the go-to standard in asynchronous logic design, the ACT suite, published by the Yale AVLSI group \citationneeded. While previous attempts have partially integrated with it \citationneeded, significant progress, such as a new simulator \citationneeded, has been made in the base toolchain. Additionally, the old tool was more of an adapter between ACT and the original workflow \citationneeded, which we feel can be improved. \\
Second, the previous tool does not account for the potential complexity of knock-on effects a given signal might have in the grander scheme of the \ac{dut}. Average insertion density is used as a stand-in metric to determine whether or not enough tests have been performed. We feel this can be improved upon using a more sophisticated stochastic framework.
\subsection{Types of failure behavior}
Points to talk about
\begin{itemize}
\item types of failures observed at the output
\end{itemize}
\subsection{Discussion of Pipeline Load Factor}
Points to talk about
\begin{itemize}
\item when does PLF make sense to begin with
\item when does it not make sense
\item (why have we not really included it in this analysis)
\end{itemize}
These failure modes are in accordance with the potential states of a circuit from \cite{bainbridgeGlitchSensitivityDefense2009}; we thus reuse the same failure classification as already presented in \cite{behalExplainingFaultSensitivity2021}.
\subsection{Injection Strategy}
Points to talk about
To improve our failure detection per simulated injection, we aim to target our simulation efforts based on signal fanout. We use this metric for both signal selection prioritization (if the injector is not set to select all signals), as well as for determining the number of injections necessary for a given signal. This is counter to previous efforts \cite{behalExplainingFaultSensitivity2021,schwendingerEvaluationDifferentTools2022a}.
\begin{itemize}
\item fault distribution: skewed by node fanout instead of average injection density
\item talk about token collector's problem and certainty of coverage, Markov inequality\dots
\item how does runtime scale with circuit size, linear with number of nodes
\end{itemize}
Signal selection is based on weighted reservoir sampling \cite{efraimidisWeightedRandomSampling2006}, with their weight being randomness with exponential falloff given their fanout, $R^{\tilde{F}}$,
where $R$ is uniformly random and $\tilde{F}$ is the normalized fanout of the signal.
To calculate the number of required injections per signal, we use the Token Collector's problem. The tool is set to expect a set number of failure modes per node fanout (tokens). From this, we first calculate the expected number of required injections, then use the Markov inequality to bound this number to a specified probability of finding all tokens.
\begin{align}
E(T) = n H_n \\
P(T \geq c n H_n) \leq \frac{1}{c}
\end{align}
where $n$ represents the number of expected failure modes per fanout, $T$ is the total required number of draws to collect all tokens, and $H_n$ is the $n$th harmonic number. Reforming this leads to the total number of expected injections $T^*$ being calculated as
\begin{align}
T^* = n H_n \cdot \frac{1}{(1 - P_{cov}) \cdot P_{hit}}
\end{align}
where $P_{hit}$ additionally describes the probability of an injection hitting a sensitive window. We have set this value to $0.001$ based on previous experiments \cite{behalExplainingFaultSensitivity2021}. As this number is calculated per selected signal, the number of required injections grows linearly with the number of signals selected (given identical fanout over all) and approximately $n\log n$ over fanout per signal.
% should we maybe put this a bit further up the paper? I mean we want this to be the main point, no?
\section{Proposed Fault-Injection Tool}
Points to talk about
@ -170,6 +196,7 @@ Points to talk about
\item changes to actsim? Addition of value overriding, addition of delay overriding; Addition of bounded stochastic delay?
\item Using dflowmap means we can easily target different families of asynchronous circuits and even synchronous circuits and compare
\item results database and post-processing
\item single event delay (if we want to throw that in)
\end{itemize}
\section{Experiment Setup}

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%\definecolor{softred}{RGB}{219,90,81}
\begin{tikzpicture}
\sffamily
\def\ns{0.85 cm};
\tikzstyle{round}=[circle, draw, minimum width = \ns, minimum height=\ns]
\tikzstyle{fork}=[circle, fill, minimum size = 0.2cm, inner sep=0pt]
\node[round] (A) {A};
\node[fork, right=2cm of A] (F) {};
\node[fork, left=2cm of C] (F2) {};
\node[round, right=2cm of F] (B) {B};
\node[round, below=1cm of B, fill=red] (C) {C};
\node[round, below=1cm of C, fill=red] (D) {D};
\draw[-] (A) -- (F);
\draw[-] (F) -- (B);
\draw[-] (F.center |- C.west) -- (C.west);
\draw[-] (F.center) -- (F.center |- D.west) -- (D.west);
\node at (A.east) [right, yshift=0.2cm] {\scriptsize outputs 1};
\node at (B.west) [left, yshift=0.2cm] {\scriptsize receives 1};
\node at (C.west) [left, yshift=0.2cm] {\scriptsize receives 0};
\node at (D.west) [left, yshift=0.2cm] {\scriptsize receives 0};
\node at (C.east) [right] {\scriptsize SET at C};
\node at (D.east) [right] {\scriptsize SET at D};
\end{tikzpicture}

30
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@ -0,0 +1,30 @@
%\definecolor{softred}{RGB}{219,90,81}
\begin{tikzpicture}
\sffamily
\def\ns{0.85 cm};
\tikzstyle{round}=[circle, draw, minimum width = \ns, minimum height=\ns]
\tikzstyle{fork}=[circle, fill, minimum size = 0.2cm, inner sep=0pt]
\node[round] (A) {A};
\node[fork, right=2cm of A] (F) {};
\node[round, right=2cm of F] (B) {B};
\node[round, below=1cm of B, fill=red] (C) {C};
\node[fork, left=2cm of C] (F2) {};
\node[round, below=1cm of C] (D) {D};
\draw[-] (A) -- (F);
\draw[-] (F) -- (B);
\draw[-] (F.center |- C.west) -- (C.west);
\draw[-] (F.center) -- (F.center |- D.west) -- (D.west);
\node at (A.east) [right, yshift=0.2cm] {\scriptsize outputs 1};
\node at (B.west) [left, yshift=0.2cm] {\scriptsize receives 1};
\node at (C.west) [left, yshift=0.2cm] {\scriptsize receives 0};
\node at (D.west) [left, yshift=0.2cm] {\scriptsize receives 1};
\node at (C.east) [right] {\scriptsize SET at C};
\end{tikzpicture}