finish introduction draft for new paper outline

fault_injection_async25.tex

@@ -15,6 +15,7 @@
 
 % Acronyms for the document
 \newacronym{dut}{DUT}{Design Under Test}
+\newacronym{api}{API}{Application Programming Interface}
 
 % Simple citation required command
 \newcommand{\citationneeded}{\textcolor{red}{[citation needed]}}
@@ -59,7 +60,10 @@ As a leading toolchain for asynchronous logic development, ACT offers a comprehe
 
 These innovations eliminate the need for additional injection-related logic within the design while also reducing development effort, as testing infrastructure for behavioral validation can simply be reused. Additionally, only the design under test needs simulation at the gate-level, while the auxiliary testing harness can stay at higher levels of abstraction. Finally, we also achieve a reduction in necessary injections by targeting high-fanout signals more heavily, discovering more faults per injection. 
 
-To validate our setup, we benchmarked it against existing fault-injection tools, demonstrating substantial improvements in both simulation efficiency and the overall number of injections needed to achieve representative results, thus enabling better scaling as target designs grow more complex.
+To validate our setup, we benchmarked it against existing fault-injection tools, demonstrating its performance in both simulation efficiency and the overall number of injections needed to achieve representative results.
+
+% Alternate abstract after test results
+% To validate our setup, we benchmarked it against existing fault-injection tools, demonstrating substantial improvements in both simulation efficiency and the overall number of injections needed to achieve representative results, thus enabling better scaling as target designs grow more complex.
 \end{abstract}
 
 \begin{IEEEkeywords}
@@ -68,16 +72,30 @@ NEEDS TO BE CHANGED
 
 \section{Introduction}
 
-Exposing digital circuits to environments like space can break some of the most basic assumptions we make when designing digital circuits. Given the level of miniaturization we have access to, having high energy particles rain upon the millions of interconnects in an average design can introduce unexpected behavior. These undesired deviations from design specification, or \emph{failures}, need to be well understood about a design's robustness.
+To make new things, we require tools. But while commercial tools offer access to the current state of the industry, they are usually not customizable enough (as they tend to be closed source) or - for more specialized applications - not available altogether. This problem is well understood for asynchronous logic, as the commercial offerings' focus on synchronous designs limits functionality for everything outside their scope. And while many of these problems have been mitigated by the publication of the open source ACT toolchain by the Yale AVLSI group \citationneeded, local compute often does not suffice for tasks that are more complex. 
 
-Synchronizing logic to a clock cycle, while potentially compromising on average case performance compared to asynchronous logic, has the helpful side-effect of creating a temporal mask for logic faults. This means that when an erroneous value is induced in a wire, only a small window of time exists where this value can propagate beyond the next logic buffer. \\
+Especially for those that lend themselves nicely to a high degree of parallelization, cluster computing offers high potential speed improvements. For this reason, we have built a tool which does just that - while offering a simple \acs{api} to vastly extend its functionality. Our goal was to create a framework to build on, and we here present a real world use-case to demonstrate this capability.
+
+Exposing digital circuits to environments like space can break some of the most basic assumptions we make when designing digital circuits. Given the level of miniaturization we have access to, having high energy particles rain upon the millions of interconnects in an average design can introduce unexpected behavior. These undesired deviations from design specification, or \emph{failures}, need to be well understood to make predictions about a design's robustness.
+
+Synchronizing logic to a clock cycle, while potentially compromising on average case performance, has the helpful side-effect of creating a temporal mask for logic faults. This means that when an erroneous value is induced in a wire, only a small window of time exists where this value can propagate beyond the next logic buffer. \\
 In asynchronous logic, we unfortunately lack this convenient abstraction. While we assume temporal masking to also play a much less obvious role in asynchronous logic \citationneeded, environmentally induced faults are still a much higher potential risk compared to a clock synchronized design. 
 
-But what is often much more important than knowing \emph{if} a design can fail under certain (extreme) circumstances, is \emph{how} exactly these failure modes play out. Certain use-cases might call for or even enforce safety in form of known failure modes on systems which are critical given their area of application. While multiple attempts have been made to create tooling for exploration of fault-space in the past \citationneeded, as of yet these tools have several shortcomings we feel need to be addressed. \\
+But what is often much more important than knowing \emph{if} a design can fail under certain (extreme) circumstances, is \emph{how} exactly these failure modes play out. Certain use-cases might call for or even enforce safety in form of known failure modes on critical systems. While multiple attempts have been made to create tooling for exploration of fault-space in the past \citationneeded, as of yet these tools have several shortcomings, which we feel need to be addressed.
+
+\section{Related Work}
+
+This work sits between two major topics.
+
+First 
+
+Second, the ACT toolchain by the Yale AVLSI group \citationneeded serves as the base toolset we are adding to
+
+ACT is second because we can talk about actsim and prsim, what advantages are there to actism over prsim
+
 First, these tools should be natively part of the toolchain slowly emerging as the go-to standard in asynchronous logic design, the ACT suite, published by the Yale AVLSI group \citationneeded. While previous attempts have partially integrated with it \citationneeded, significant progress, such as a new simulator \citationneeded, has been made in the base toolchain. Additionally, the old tool was more of an adapter between ACT and the original workflow \citationneeded, which we feel can be improved. \\
 Second, the previous tool does not account for the potential complexity of knock-on effects a given signal might have in the grander scheme of the \ac{dut}. Average insertion density is used as a stand-in metric to determine whether or not enough tests have been performed. We feel this can be improved upon using a more sophisticated stochastic framework.
 
-\section{Related Work}
 
 Points to talk about
 
@@ -87,7 +105,7 @@ Points to talk about
     \item what fault model did they use
 \end{itemize}
 
-\section{Fault Model}
+\section{System Model}
 
 \subsection{On fault nomenclature}