finished first draft related work
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@ -19,7 +19,7 @@
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author = {Behal, Patrick and Huemer, Florian and Najvirt, Robert and Steininger, Andreas},
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month = sep,
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year = {2021},
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keywords = {asynchronous circuits, Circuit faults, Data models, Databases, fault injection, fault-tolerance assessment, Integrated circuit modeling, Pipelines, Task analysis, tool chain, Tools},
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keywords = {Databases, Circuit faults, Pipelines, Integrated circuit modeling, asynchronous circuits, Data models, fault injection, fault-tolerance assessment, Task analysis, tool chain, Tools},
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pages = {541--548},
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file = {Behal et al_2021_An Automated Setup for Large-Scale Simulation-Based Fault-Injection Experiments.pdf:/home/fabian/Zotero/storage/P2Z8XV9J/Behal et al_2021_An Automated Setup for Large-Scale Simulation-Based Fault-Injection Experiments.pdf:application/pdf;IEEE Xplore Abstract Record:/home/fabian/Zotero/storage/J2YJQQEM/9556468.html:text/html},
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}
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@ -110,3 +110,90 @@
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Journal Abbreviation: Evaluierung von verschiedenen Tools für Design und Fehlerinjektion von Asynchronen Schaltungen},
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file = {Full Text PDF:/home/fabian/Zotero/storage/9EBJ7BI9/Schwendinger - 2022 - Evaluation of different tools for design and fault-injection of asynchronous circuits.pdf:application/pdf},
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}
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@inproceedings{monnet_asynchronous_2004,
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title = {Asynchronous circuits sensitivity to fault injection},
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url = {https://ieeexplore.ieee.org/abstract/document/1319669?casa_token=VzWq30-c2KEAAAAA:iDAIQCcGlCTDf9fbAiuJeL0NKzlNQDn8cBCyOK9zdUbdB9XBDNecWy2UTW9j37SJ-xMoMNGjQQ},
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doi = {10.1109/OLT.2004.1319669},
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abstract = {This paper presents an analysis of the faults sensitivity of Quasi Delay Insensitive (QDI) asynchronous circuits. Faults considered in this work can be either natural or intentional. However, fault injection attacks which consist in causing an intentional temporary dysfunction of a circuit by injecting faults in its combinational or sequential parts are of prime interest. This failure enables hackers to access protected memory areas or secret information like cryptographic keys. This work focuses on analysing the sensitivity of asynchronous circuits to fault injection. A circuit fault-sensitivity criterion is defined, which enables to point out weak parts of the circuits in order to specify hardening strategies.},
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urldate = {2025-01-04},
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booktitle = {Proceedings. 10th {IEEE} {International} {On}-{Line} {Testing} {Symposium}},
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author = {Monnet, Y. and Renaudin, M. and Leveugle, R.},
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month = jul,
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year = {2004},
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keywords = {Delay, Laboratories, Protocols, Circuit faults, Clocks, Asynchronous circuits, Computer hacking, Cryptography, Protection, Smart cards},
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pages = {121--126},
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file = {Full Text PDF:/home/fabian/Zotero/storage/PQULARRY/Monnet et al. - 2004 - Asynchronous circuits sensitivity to fault injection.pdf:application/pdf;IEEE Xplore Abstract Record:/home/fabian/Zotero/storage/BSZIZQ4S/1319669.html:text/html},
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}
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@inproceedings{bainbridge_glitch_2009,
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title = {Glitch {Sensitivity} and {Defense} of {Quasi} {Delay}-{Insensitive} {Network}-on-{Chip} {Links}},
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url = {https://ieeexplore.ieee.org/abstract/document/5010334},
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doi = {10.1109/ASYNC.2009.18},
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abstract = {To the casual observer, glitches occurring in quasi delay-insensitive logic would appear to cause incorrect operation and render the circuits unusable. This paper presents an informal analysis of the effects of glitches occurring on the long interconnect wires connecting logical units of a network-on-chip (NoC) using quasi delay-insensitive (QDI) techniques. This is followed by the introduction and analysis of a set of techniques to reduce the likelihood and impact of such hazards affecting the circuit. Post layout area and performance impacts are presented for a 90 nm process.},
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urldate = {2025-01-04},
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booktitle = {2009 15th {IEEE} {Symposium} on {Asynchronous} {Circuits} and {Systems}},
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author = {Bainbridge, William John and Salisbury, Sean James},
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month = may,
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year = {2009},
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note = {ISSN: 1522-8681},
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keywords = {Pipelines, Asynchronous circuits, QDI, Asynchronous, Delay effects, Delay Insensitive, Electromagnetic coupling, Electromagnetic interference, Glitch, Hazard, Hazards, Integrated circuit interconnections, Logic circuits, Network-on-a-chip, Network-on-Chip, NoC, Wires},
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pages = {35--44},
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file = {Full Text PDF:/home/fabian/Zotero/storage/S63EJBW8/Bainbridge and Salisbury - 2009 - Glitch Sensitivity and Defense of Quasi Delay-Insensitive Network-on-Chip Links.pdf:application/pdf;IEEE Xplore Abstract Record:/home/fabian/Zotero/storage/CT84FYAU/5010334.html:text/html},
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}
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@inproceedings{jang_seu-tolerant_2005,
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title = {{SEU}-tolerant {QDI} circuits [quasi delay-insensitive asynchronous circuits]},
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url = {https://ieeexplore.ieee.org/abstract/document/1402057},
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doi = {10.1109/ASYNC.2005.30},
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abstract = {This paper addresses the issue of single-event upset (SEU) in quasi delay-insensitive (QDI) asynchronous circuits. We show that an SEU can cause abnormal computations in QDI circuits beside deadlock, and we propose a general method to make QDI circuits SEU-tolerant. We present simplified SEU-tolerant buffer implementations for CMOS technology. Finally, we present a case study of a one-bit comparator and show SPICE-simulation results.},
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urldate = {2025-01-04},
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booktitle = {11th {IEEE} {International} {Symposium} on {Asynchronous} {Circuits} and {Systems}},
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author = {Jang, Wonjin and Martin, A.J.},
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month = mar,
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year = {2005},
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note = {ISSN: 1522-8681},
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keywords = {Circuits},
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pages = {156--165},
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file = {Full Text PDF:/home/fabian/Zotero/storage/2UE6RWYF/Jang and Martin - 2005 - SEU-tolerant QDI circuits [quasi delay-insensitive asynchronous circuits].pdf:application/pdf;IEEE Xplore Abstract Record:/home/fabian/Zotero/storage/2FJ74JFH/1402057.html:text/html},
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}
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@inproceedings{mcgee_level-encoded_2008,
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title = {A {Level}-{Encoded} {Transition} {Signaling} {Protocol} for {High}-{Throughput} {Asynchronous} {Global} {Communication}},
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url = {https://ieeexplore.ieee.org/abstract/document/4557004},
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doi = {10.1109/ASYNC.2008.24},
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abstract = {A new delay-insensitive data encoding scheme for global communication, level-encoded transition signaling (LETS), is introduced. LETS is a generalization of level-encoded dual rail (LEDR), an earlier non-return-to-zero encoding scheme where one of two wires changes value per data bit per transaction. In LETS, only one of N = 2n (1-of-N) wire changes value per n data bits per transaction. Compared to most common return-to-zero encoding schemes, LETS has potential power and throughput advantages, since fewer rails switch and no return-to-zero phase is required. Compared to existing nonreturn-to-zero schemes (i.e., LEDR), higher-dimension LETS codes have a potential power advantage, with significantly reduced switching activity per data bit.Two alternative 1-of-4 LETS codes are proposed, and efficient hardware for completion detection and conversion to return-to-zero protocols is introduced. Finally, a general theoretical framework is presented which characterizes the properties of arbitrary 1-of-N LETS codes, as well as a simple procedure to generate such codes.},
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urldate = {2025-01-04},
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booktitle = {2008 14th {IEEE} {International} {Symposium} on {Asynchronous} {Circuits} and {Systems}},
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author = {McGee, Peggy B. and Agyekum, Melinda Y. and Mohamed, Moustafa A. and Nowick, Steven M.},
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month = apr,
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year = {2008},
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note = {ISSN: 1522-8681},
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keywords = {Throughput, Hardware, Character generation, Delay, Switches, Encoding, Protocols, Rails, Wires, Global communication},
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pages = {116--127},
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file = {Full Text PDF:/home/fabian/Zotero/storage/6ACGIVSX/McGee et al. - 2008 - A Level-Encoded Transition Signaling Protocol for High-Throughput Asynchronous Global Communication.pdf:application/pdf;IEEE Xplore Abstract Record:/home/fabian/Zotero/storage/U73E7C33/4557004.html:text/html},
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}
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@inproceedings{vezzoli_designing_2024,
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title = {Designing an {Energy}-{Efficient} {Fully}-{Asynchronous} {Deep} {Learning} {Convolution} {Engine}},
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url = {https://ieeexplore.ieee.org/abstract/document/10546579?casa_token=oOEtwQgdhy0AAAAA:qgIlHzgpaATvA0I_s_f17d7l-Y4_hs-yesK6eY4Yg0Fa-M0dh7N0YqtFDsY0gNYQ934XrzYIgg},
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doi = {10.23919/DATE58400.2024.10546579},
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abstract = {In the face of exponential growth in semiconductor energy usage, there is a significant push towards highly energy-efficient microelectronics design. While the traditional circuit designs typically employ clocks to synchronize the computing operations, these circuits incur significant performance and energy overheads due to their data-independent worst-case operation and complex clock tree networks. In this paper, we explore asynchronous or clockless techniques where clocks are replaced by request, acknowledge handshaking signals. To quantify the potential energy and performance gains of asynchronous logic, we design a highly energy -efficient asynchronous deep learning convolution engine, which uses 87 \% of total DL accelerator energy. Our asynchronous design shows 5.06x lower energy and 5.09 x lower delay than the synchronous one.},
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urldate = {2025-01-04},
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booktitle = {2024 {Design}, {Automation} \& {Test} in {Europe} {Conference} \& {Exhibition} ({DATE})},
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author = {Vezzoli, Mattia and Nel, Lukas and Bhardwaj, Kshitij and Manohar, Rajit and Gokhale, Maya},
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month = mar,
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year = {2024},
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note = {ISSN: 1558-1101},
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keywords = {Protocols, Deep learning, Energy efficiency, Microelectronics, Convolution, Performance gain, Potential energy},
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pages = {1--2},
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file = {Full Text PDF:/home/fabian/Zotero/storage/ZJYHV4YF/Vezzoli et al. - 2024 - Designing an Energy-Efficient Fully-Asynchronous Deep Learning Convolution Engine.pdf:application/pdf;IEEE Xplore Abstract Record:/home/fabian/Zotero/storage/MLL9B696/10546579.html:text/html},
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}
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@article{he_interact_nodate,
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title = {interact: {An} {Interactive} {Design} {Environment} for {Asynchronous} {Logic}},
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abstract = {We are developing an open-source EDA flow for asynchronous logic. We present the current state of the flow, where all the key components have been integrated into a single framework including the timer, partitioner, placer, power detailed router, and global router. We describe enhancements to the flow in terms of the class of circuits that can be handled, and extensions to support third-party libraries and flows.},
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language = {en},
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author = {He, Jiayuan and Hua, Wenmian and Lu, Yi-Shan and Maleki, Sepideh and Yang, Yihang and Pingali, Keshav and Manohar, Rajit},
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file = {a13.pdf:/home/fabian/Zotero/storage/5G9HMT2B/a13.pdf:application/pdf},
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}
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@ -16,6 +16,9 @@
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% Acronyms for the document
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\newacronym{dut}{DUT}{Design Under Test}
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\newacronym{api}{API}{Application Programming Interface}
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\newacronym{wchb}{WCHB}{Weakly Conditioned Half Buffer}
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\newacronym{qdi}{QDI}{Quasi Delay Insensitive}
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\newacronym{set}{SET}{Single Event Transient}
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% Simple citation required command
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\newcommand{\citationneeded}{\textcolor{red}{[citation needed]}}
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@ -85,26 +88,17 @@ But what is often much more important than knowing \emph{if} a design can fail u
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\section{Related Work}
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The tool presented in \cite{behal_towards_2021} is a fault injection and fault space exploration tool, aiming to explore fault types in a given circuit. It is quite similar to the demo use-case we show in this paper. It distinguishes fault classes \emph{timing deviation}, \emph{value fault}, \emph{code fault}, \emph{glitch}, \emph{deadlock}, and \emph{token count error}, which are largely reused for this paper (more on our system model in Section \ref{sec:system_model}). The core simulator used is QuestaSim (version 10.6c), which is a commercial simulation tool. To reduce the runtime of one simulation, a cluster based approach is employed to parallelize simulations over multiple machines. This tool has been designed for the \texttt{pypr} toolchain designed by the Huemer at TU Wien \cite{huemer_contributions_2022}, a production rule based circuit description framework in Python. Notably, the system calculates the number of required injections using a system of average injection density, independently of which signal it is targeting.\\
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\texttt{action} is an addition to the ACT toolchain initially presented in \cite{manohar_open_2019}. ACT aims to be a collection of tools for an end-to-end chip design workflow. While the main focus of its tools is asynchronous designs, it is powerful enough to also map to synchronous logic families without issue \cite{vezzoli_designing_2024}. The current version of the ACT toolflow does include a scripting environment \cite{he_interact_nodate}, it does however not contain a solution for distributed computing tasks, which would be helpful for testing and verification tasks.
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Focusing on our specific demo use-case, the tool presented in \cite{behal_towards_2021} is a fault injection and fault space exploration tool, aiming to explore fault types in a given circuit. It is quite similar to the demo use-case we show in this paper. It distinguishes fault classes \emph{timing deviation}, \emph{value fault}, \emph{code fault}, \emph{glitch}, \emph{deadlock}, and \emph{token count error}, which are largely reused for this paper (more on our system model in Section \ref{sec:system_model}). The core simulator used is QuestaSim (version 10.6c), which is a commercial simulation tool. To reduce the runtime of one simulation, a cluster based approach is employed to parallelize simulations over multiple machines. This tool has been designed for the \texttt{pypr} toolchain designed by the Huemer at TU Wien \cite{huemer_contributions_2022}, a production rule based circuit description framework in Python. Notably, the system calculates the number of required injections using a system of average injection density, independently of which signal it is targeting. This is one of the main points on which we will try to improve upon.\\
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% should i include work in master thesis?
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An iteration of this system can be found in \cite{schwendinger_evaluation_2022}. While based on the same core toolflow, Behal adds limited bridging logic to the ACT toolchain, using \textrm{prsim} \cite{manohar_open_2019} as an alternative simulator.
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\\\\
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An iteration of this system can be found in \cite{schwendinger_evaluation_2022}. While based on the same core toolflow, Behal adds limited bridging logic to the ACT toolchain, using \textrm{prsim} \cite{manohar_open_2019} as an alternative simulator. This change requires low level simulation of additional logic, as certain required features were not supported by \texttt{prsim} and no extension to the core simulator code was written. This again is a major point for potential improvement.
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Second, the ACT toolchain by the Yale AVLSI group \citationneeded serves as the base toolset we are adding to
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Finally, we want to briefly touch on different fault-mitigation techniques seen in literature. \\
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Bainbridge and Salisbury \cite{bainbridge_glitch_2009} talks about the basic possibilities for fault behavior in \ac{qdi} circuits. Much like \cite{behal_towards_2021}, it identifies specific scenarios which can occur when a \ac{set} is injected into a circuit. We will come back to this in Section \ref{sec:system_model} as well. It then lays out basic mitigation techniques, which largely focus on either introducing some form of redundancy in the circuit or reducing the temporal size of the window in which faults are converted into failure behavior (sensitivity window).
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ACT is second because we can talk about actsim and prsim, what advantages are there to actism over prsim
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In a similar fashion, Huemer et.al \cite{huemer_identification_2020} presents interlocking and deadlocking versions of a \ac{wchb}. These are also meant to reduce the sensitivity window size, as well as preventing the propagation of illegal symbols. We will use their implementations for interlocking and deadlocking \acp{wchb} in this paper (more in Section \ref{sec:experiment_setup}).
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First, these tools should be natively part of the toolchain slowly emerging as the go-to standard in asynchronous logic design, the ACT suite, published by the Yale AVLSI group \citationneeded. While previous attempts have partially integrated with it \citationneeded, significant progress, such as a new simulator \citationneeded, has been made in the base toolchain. Additionally, the old tool was more of an adapter between ACT and the original workflow \citationneeded, which we feel can be improved. \\
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Second, the previous tool does not account for the potential complexity of knock-on effects a given signal might have in the grander scheme of the \ac{dut}. Average insertion density is used as a stand-in metric to determine whether or not enough tests have been performed. We feel this can be improved upon using a more sophisticated stochastic framework.
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Points to talk about
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\begin{itemize}
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\item ACT toolchain in a nutshell
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\item previous works by TU Wien
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\item what fault model did they use
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\end{itemize}
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\section{System Model}
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\label{sec:system_model}
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\item single event delay (if we want to throw that in)
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\end{itemize}
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Talk about fault outcomes in \cite{bainbridge_glitch_2009}
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\subsection{Per-Node Fault Space}
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\item show some graphs for this
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\end{itemize}
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First, these tools should be natively part of the toolchain slowly emerging as the go-to standard in asynchronous logic design, the ACT suite, published by the Yale AVLSI group \citationneeded. While previous attempts have partially integrated with it \citationneeded, significant progress, such as a new simulator \citationneeded, has been made in the base toolchain. Additionally, the old tool was more of an adapter between ACT and the original workflow \citationneeded, which we feel can be improved. \\
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Second, the previous tool does not account for the potential complexity of knock-on effects a given signal might have in the grander scheme of the \ac{dut}. Average insertion density is used as a stand-in metric to determine whether or not enough tests have been performed. We feel this can be improved upon using a more sophisticated stochastic framework.
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\subsection{Types of failure behavior}
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Points to talk about
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\end{itemize}
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\section{Experiment Setup}
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\label{sec:experiment_setup}
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Points to talk about
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