From 4e4f1205e0ed3f2482522a75ae05944a9c543886 Mon Sep 17 00:00:00 2001
From: Fabian Posch <fabian@posch.tech>
Date: Mon, 9 Dec 2024 20:31:06 +0100
Subject: [PATCH] add paper outline

---
 fault_injection_async25.tex | 103 +++++++++++++++++++++++++++++++++++-
 1 file changed, 102 insertions(+), 1 deletion(-)

diff --git a/fault_injection_async25.tex b/fault_injection_async25.tex
index 8bbd148..b8b7813 100644
--- a/fault_injection_async25.tex
+++ b/fault_injection_async25.tex
@@ -54,7 +54,108 @@ In this paper we present an augmentation of ACT which allows flexible and compre
 NEEDS TO BE CHANGED
 \end{IEEEkeywords}
 
-This is a test reference for the paper \cite{altera_introduction_2013}
+\section{Introduction}
+
+Points to talk about
+
+\begin{itemize}
+    \item what is the problem to begin with
+    \item why should one care
+    \item what is temporal masking
+    \item why does async not have this luxury
+\end{itemize}
+
+\section{Related Work}
+
+Points to talk about
+
+\begin{itemize}
+    \item ACT toolchain in a nutshell
+    \item previous works by TU Wien
+    \item what fault model did they use
+\end{itemize}
+
+\section{Fault Model}
+
+\subsection{On fault nomenclature}
+
+Points to talk about
+
+\begin{itemize}
+    \item different types of faults that can occur
+    \item upset vs transient
+    \item single event delay (if we want to throw that in)
+\end{itemize}
+
+\subsection{Per-Node Fault Space}
+
+Points to talk about
+
+\begin{itemize}
+    \item fault is injected as output from one node diverges from specification
+    \item show why this makes sense: only certain input combinations would activate a gate in a way where it could create erroneous output; everything else is logically masked $\rightarrow$ simulation doesn't make sense anyway
+    \item which fault scenarios can and cannot be simulated
+    \item show some graphs for this
+\end{itemize}
+
+\subsection{Types of failure behavior}
+
+Points to talk about
+
+\begin{itemize}
+    \item types of failures observed at the output
+\end{itemize}
+
+\subsection{Discussion of Pipeline Load Factor}
+
+Points to talk about
+
+\begin{itemize}
+    \item when does PLF make sense to begin with
+    \item when does it not make sense
+    \item why have we not really included it in this analysis
+\end{itemize}
+
+\subsection{Injection Strategy}
+
+Points to talk about
+
+\begin{itemize}
+    \item fault distribution: skewed by node fanout instead of average injection density
+\end{itemize}
+
+\section{Experiment Setup}
+
+Points to talk about
+
+\begin{itemize}
+    \item what was the target circuit
+\end{itemize}
+
+\subsection{Tooling}
+
+Points to talk about
+
+\begin{itemize}
+    \item workflow: setup of harness, similarity to UVM, testbench design intended as design once, use for entire verification workflow
+    \item why is this better than before? Performance improvements, not everything is simulated at gate level anymore, actsim is a mixed level simulator; DUT is simulated at gate level, while harness is simulated at higher level of abstraction
+    \item changes to actsim? Addition of value overriding, addition of delay overriding; Addition of bounded stochastic delay?
+    \item Using dflowmap means we can easily target different families of asynchronous circuits and even synchronous circuits and compare
+    \item results database and post-processing
+\end{itemize}
+
+\section{Results}
+
+Points to talk about
+
+\begin{itemize}
+    \item how many failures were we able to find with our new tool vs with the old tool
+    \item how efficient (failures found / injection) is this setup compared to previous attempts
+    \item how do certain families of async and sync compare
+\end{itemize}
+
+\section{Conclusion}
+
 
 \printbibliography