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actual testbench

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Fabian Posch 2025-02-02 22:59:55 +01:00
parent 4784ebb8ba
commit 4891ebe5c6
3 changed files with 7 additions and 6 deletions
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3
test-circuit/mult_wrapper.act
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@ -1,5 +1,5 @@
import "umul4x4_nodelay.act";
import "prs/umul4x4_DIMS.act";
import std::data;
import "minichannel.act";
import "globals.act";
@ -16,5 +16,6 @@ defproc pipelined_mult(aMx1of2?<4> A, B; aMx1of2!<8> RES) {
mult.b = B.d.d;
A.a = mult.ack_out;
B.a = mult.ack_out;
mult.reset = Reset;
}

4
test-circuit/simlib.act
View file

@ -50,8 +50,8 @@ defproc lockstep (chan?(int<IN_D_WIDTH>) IN[IN_CHANNELS]; chan?(int<OUT_D_WIDTH>
*[
// receive the data
(, i : IN_CHANNELS : IN[i]?input[i]),
(, i : OUT_CHANNELS : OUT_M[i]?output_m[i]),
(, j : OUT_CHANNELS : OUT_D[j]?output_d[j]);
(, i : OUT_CHANNELS : (OUT_M[i]?output_m[i]; log("Model response received, channel ", i))),
(, j : OUT_CHANNELS : (OUT_D[j]?output_d[j]; log("DUT response received, channel ", j)));
// check the results
not_failed+;

6
test-circuit/testbench.act
View file

@ -22,11 +22,11 @@ defproc tb() {
pint IN_WIDTH = 4;
pint OUT_WIDTH = 8;
pint IN_SEQ_L = 8;
pint IN_SEQ_L = 5;
pint in_seq_a[IN_SEQ_L];
pint in_seq_b[IN_SEQ_L];
in_seq_a = {7, 6, 5, 1, 2, 3, 0, 4};
in_seq_b = {4, 0, 3, 2, 1, 5, 6, 7};
in_seq_a = {7, 6, 5, 1, 3};
in_seq_b = {4, 0, 3, 5, 9};
// model and DUT
mul_model<IN_WIDTH, OUT_WIDTH> model;